/dports/emulators/aranym/aranym-1.1.0/src/uae_cpu/fpu/ |
H A D | flags.h | 186 uae_u32 fpccr = 0; in get_fpccr() local 188 fpccr |= FPSR_CCB_NAN; in get_fpccr() 190 fpccr |= FPSR_CCB_INFINITY; in get_fpccr() 192 fpccr |= FPSR_CCB_ZERO; in get_fpccr() 194 fpccr |= FPSR_CCB_NEGATIVE; in get_fpccr() 195 return fpccr; in get_fpccr()
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/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
H A D | m_helper.c | 407 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER() 978 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr() 979 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr() 980 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local 992 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr() 995 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); in v7m_update_fpccr() 999 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); in v7m_update_fpccr() 1001 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, in v7m_update_fpccr() 1011 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); in v7m_update_fpccr() 1031 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER() [all …]
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/dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
H A D | m_helper.c | 409 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER() 981 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr() 982 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr() 983 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local 995 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr() 998 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); in v7m_update_fpccr() 1002 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); in v7m_update_fpccr() 1004 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, in v7m_update_fpccr() 1014 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); in v7m_update_fpccr() 1034 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER() [all …]
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H A D | machine.c | 313 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
H A D | m_helper.c | 407 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER() 979 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr() 980 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr() 981 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local 993 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr() 996 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); in v7m_update_fpccr() 1000 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); in v7m_update_fpccr() 1002 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, in v7m_update_fpccr() 1012 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); in v7m_update_fpccr() 1032 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER() [all …]
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H A D | machine.c | 313 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
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/dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
H A D | m_helper.c | 407 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER() 978 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr() 979 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr() 980 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local 992 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr() 995 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); in v7m_update_fpccr() 999 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); in v7m_update_fpccr() 1001 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, in v7m_update_fpccr() 1011 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); in v7m_update_fpccr() 1031 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER() [all …]
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
H A D | m_helper.c | 407 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER() 979 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr() 980 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr() 981 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local 993 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr() 996 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); in v7m_update_fpccr() 1000 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); in v7m_update_fpccr() 1002 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, in v7m_update_fpccr() 1012 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); in v7m_update_fpccr() 1032 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER() [all …]
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/dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
H A D | m_helper.c | 410 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER() 994 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr() 995 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr() 996 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local 1008 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr() 1011 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); in v7m_update_fpccr() 1015 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); in v7m_update_fpccr() 1017 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, in v7m_update_fpccr() 1027 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); in v7m_update_fpccr() 1047 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER() [all …]
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H A D | cpu.c | 323 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; in arm_cpu_reset() 324 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | in arm_cpu_reset()
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H A D | machine.c | 313 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
H A D | m_helper.c | 415 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER() 1002 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr() 1003 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr() 1004 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local 1016 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr() 1019 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); in v7m_update_fpccr() 1023 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); in v7m_update_fpccr() 1025 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, in v7m_update_fpccr() 1035 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); in v7m_update_fpccr() 1056 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER() [all …]
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H A D | translate-m-nocp.c | 136 aspen = load_cpu_field(v7m.fpccr[M_REG_S]); in trans_VSCCLRM() 300 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); in gen_branch_fpInactive()
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H A D | cpu.c | 337 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; in arm_cpu_reset() 338 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | in arm_cpu_reset() 380 env->v7m.fpccr[M_REG_S] &= in arm_cpu_reset()
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/dports/emulators/qemu/qemu-6.2.0/target/arm/ |
H A D | m_helper.c | 415 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER() 1002 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr() 1003 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr() 1004 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local 1016 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr() 1019 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); in v7m_update_fpccr() 1023 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); in v7m_update_fpccr() 1025 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, in v7m_update_fpccr() 1035 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); in v7m_update_fpccr() 1056 bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER() [all …]
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H A D | translate-m-nocp.c | 136 aspen = load_cpu_field(v7m.fpccr[M_REG_S]); in trans_VSCCLRM() 300 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); in gen_branch_fpInactive()
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H A D | cpu.c | 337 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; in arm_cpu_reset() 338 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | in arm_cpu_reset() 380 env->v7m.fpccr[M_REG_S] &= in arm_cpu_reset()
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/dports/emulators/qemu42/qemu-4.2.1/hw/intc/ |
H A D | armv7m_nvic.c | 684 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp() 685 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp() local 702 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 705 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 1424 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1432 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1443 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl() 1974 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; in nvic_writel() 2000 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel() 2004 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; in nvic_writel()
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/dports/emulators/qemu/qemu-6.2.0/hw/intc/ |
H A D | armv7m_nvic.c | 697 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp() 698 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp() local 715 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 718 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 1518 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1526 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1537 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl() 2093 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; in nvic_writel() 2119 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel() 2123 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; in nvic_writel()
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/dports/emulators/qemu5/qemu-5.2.0/hw/intc/ |
H A D | armv7m_nvic.c | 699 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp() 700 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp() local 717 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 720 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 1480 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1488 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1499 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl() 2030 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; in nvic_writel() 2056 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel() 2060 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; in nvic_writel()
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/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/ |
H A D | armv7m_nvic.c | 684 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp() 685 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp() local 702 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 705 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 1424 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1432 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1443 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl() 1974 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; in nvic_writel() 2000 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel() 2004 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; in nvic_writel()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/ |
H A D | armv7m_nvic.c | 684 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; 685 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; 702 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); 705 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); 1424 return cpu->env.v7m.fpccr[M_REG_S]; 1432 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; 1443 value |= cpu->env.v7m.fpccr[M_REG_NS]; 1974 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; 2000 cpu->env.v7m.fpccr[M_REG_NS] = value; 2004 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s;
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/ |
H A D | armv7m_nvic.c | 684 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp() 685 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp() local 702 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 705 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 1424 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1432 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1443 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl() 1974 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; in nvic_writel() 2000 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel() 2004 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; in nvic_writel()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/ |
H A D | armv7m_nvic.c | 697 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp() 698 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp() local 715 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 718 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 1518 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1526 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1537 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl() 2093 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; in nvic_writel() 2119 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel() 2123 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; in nvic_writel()
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/dports/emulators/qemu60/qemu-6.0.0/hw/intc/ |
H A D | armv7m_nvic.c | 699 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp() 700 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp() local 717 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 720 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); in armv7m_nvic_set_pending_lazyfp() 1503 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1511 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl() 1522 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl() 2078 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; in nvic_writel() 2104 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel() 2108 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; in nvic_writel()
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