Home
last modified time | relevance | path

Searched refs:gicd_statusr (Results 1 – 25 of 27) sorted by relevance

12

/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A Darm_gicv3_common.c230 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
442 s->gicd_statusr[GICV3_S] = 0; in arm_gicv3_common_reset()
443 s->gicd_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset()
H A Darm_gicv3_kvm.c409 reg = s->gicd_statusr[GICV3_NS]; in kvm_arm_gicv3_put()
574 s->gicd_statusr[GICV3_NS] = reg; in kvm_arm_gicv3_get()
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Darm_gicv3_common.c230 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
442 s->gicd_statusr[GICV3_S] = 0; in arm_gicv3_common_reset()
443 s->gicd_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset()
H A Darm_gicv3_kvm.c408 reg = s->gicd_statusr[GICV3_NS]; in kvm_arm_gicv3_put()
577 s->gicd_statusr[GICV3_NS] = reg; in kvm_arm_gicv3_get()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A Darm_gicv3_common.c227 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
439 s->gicd_statusr[GICV3_S] = 0; in arm_gicv3_common_reset()
440 s->gicd_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset()
H A Darm_gicv3_kvm.c411 reg = s->gicd_statusr[GICV3_NS]; in kvm_arm_gicv3_put()
576 s->gicd_statusr[GICV3_NS] = reg; in kvm_arm_gicv3_get()
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A Darm_gicv3_common.c230 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
442 s->gicd_statusr[GICV3_S] = 0; in arm_gicv3_common_reset()
443 s->gicd_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset()
H A Darm_gicv3_kvm.c408 reg = s->gicd_statusr[GICV3_NS]; in kvm_arm_gicv3_put()
573 s->gicd_statusr[GICV3_NS] = reg; in kvm_arm_gicv3_get()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A Darm_gicv3_common.c230 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
442 s->gicd_statusr[GICV3_S] = 0; in arm_gicv3_common_reset()
443 s->gicd_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset()
H A Darm_gicv3_kvm.c409 reg = s->gicd_statusr[GICV3_NS]; in kvm_arm_gicv3_put()
574 s->gicd_statusr[GICV3_NS] = reg; in kvm_arm_gicv3_get()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A Darm_gicv3_common.c230 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2), in complement_and_test()
442 s->gicd_statusr[GICV3_S] = 0;
443 s->gicd_statusr[GICV3_NS] = 0;
H A Darm_gicv3_kvm.c409 reg = s->gicd_statusr[GICV3_NS];
574 s->gicd_statusr[GICV3_NS] = reg;
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/
H A Darm_gicv3_common.c230 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
442 s->gicd_statusr[GICV3_S] = 0; in arm_gicv3_common_reset()
443 s->gicd_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Darm_gicv3_common.c230 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
466 s->gicd_statusr[GICV3_S] = 0; in arm_gicv3_common_reset()
467 s->gicd_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset()
H A Darm_gicv3_kvm.c407 reg = s->gicd_statusr[GICV3_NS]; in kvm_arm_gicv3_put()
576 s->gicd_statusr[GICV3_NS] = reg; in kvm_arm_gicv3_get()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A Darm_gicv3_common.c230 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
452 s->gicd_statusr[GICV3_S] = 0; in arm_gicv3_common_reset()
453 s->gicd_statusr[GICV3_NS] = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu42/qemu-4.2.1/include/hw/intc/
H A Darm_gicv3_common.h235 uint32_t gicd_statusr[2]; member
/dports/emulators/qemu/qemu-6.2.0/include/hw/intc/
H A Darm_gicv3_common.h258 uint32_t gicd_statusr[2]; member
/dports/emulators/qemu60/qemu-6.0.0/include/hw/intc/
H A Darm_gicv3_common.h235 uint32_t gicd_statusr[2]; member
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/intc/
H A Darm_gicv3_common.h235 uint32_t gicd_statusr[2]; member
/dports/emulators/qemu5/qemu-5.2.0/include/hw/intc/
H A Darm_gicv3_common.h235 uint32_t gicd_statusr[2]; member
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/intc/
H A Darm_gicv3_common.h235 uint32_t gicd_statusr[2]; member
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/intc/
H A Darm_gicv3_common.h235 uint32_t gicd_statusr[2];
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/intc/
H A Darm_gicv3_common.h248 uint32_t gicd_statusr[2]; member
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/include/hw/intc/
H A Darm_gicv3_common.h235 uint32_t gicd_statusr[2]; member

12