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Searched refs:gicr_nsacr (Results 1 – 25 of 37) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A Darm_gicv3_redist.c35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
234 *data = cs->gicr_nsacr; in gicr_readl()
361 cs->gicr_nsacr = value; in gicr_writel()
H A Darm_gicv3_common.c165 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
425 cs->gicr_nsacr = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A Darm_gicv3_redist.c35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
234 *data = cs->gicr_nsacr; in gicr_readl()
361 cs->gicr_nsacr = value; in gicr_writel()
H A Darm_gicv3_common.c165 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
425 cs->gicr_nsacr = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A Darm_gicv3_redist.c35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
234 *data = cs->gicr_nsacr; in gicr_readl()
361 cs->gicr_nsacr = value; in gicr_writel()
H A Darm_gicv3_common.c162 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
422 cs->gicr_nsacr = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A Darm_gicv3_redist.c35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
234 *data = cs->gicr_nsacr; in gicr_readl()
361 cs->gicr_nsacr = value; in gicr_writel()
H A Darm_gicv3_common.c165 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
425 cs->gicr_nsacr = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A Darm_gicv3_redist.c35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
234 *data = cs->gicr_nsacr; in gicr_readl()
361 cs->gicr_nsacr = value; in gicr_writel()
H A Darm_gicv3_common.c165 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
425 cs->gicr_nsacr = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A Darm_gicv3_redist.c35 return extract32(cs->gicr_nsacr, irq * 2, 2);
234 *data = cs->gicr_nsacr;
361 cs->gicr_nsacr = value;
H A Darm_gicv3_common.c165 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState), in fetch_complement()
425 cs->gicr_nsacr = 0;
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/
H A Darm_gicv3_redist.c35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
234 *data = cs->gicr_nsacr; in gicr_readl()
361 cs->gicr_nsacr = value; in gicr_writel()
H A Darm_gicv3_common.c165 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
425 cs->gicr_nsacr = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A Darm_gicv3_redist.c35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
234 *data = cs->gicr_nsacr; in gicr_readl()
371 cs->gicr_nsacr = value; in gicr_writel()
H A Darm_gicv3_common.c165 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
448 cs->gicr_nsacr = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A Darm_gicv3_redist.c35 return extract32(cs->gicr_nsacr, irq * 2, 2);
234 *data = cs->gicr_nsacr;
370 cs->gicr_nsacr = value;
H A Darm_gicv3_common.c165 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
434 cs->gicr_nsacr = 0; in arm_gicv3_common_reset()
/dports/emulators/qemu42/qemu-4.2.1/include/hw/intc/
H A Darm_gicv3_common.h173 uint32_t gicr_nsacr; member
/dports/emulators/qemu/qemu-6.2.0/include/hw/intc/
H A Darm_gicv3_common.h175 uint32_t gicr_nsacr; member
/dports/emulators/qemu60/qemu-6.0.0/include/hw/intc/
H A Darm_gicv3_common.h173 uint32_t gicr_nsacr; member
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/intc/
H A Darm_gicv3_common.h173 uint32_t gicr_nsacr; member
/dports/emulators/qemu5/qemu-5.2.0/include/hw/intc/
H A Darm_gicv3_common.h173 uint32_t gicr_nsacr; member
/dports/emulators/qemu-utils/qemu-4.2.1/include/hw/intc/
H A Darm_gicv3_common.h173 uint32_t gicr_nsacr; member
/dports/emulators/qemu-guest-agent/qemu-5.0.1/include/hw/intc/
H A Darm_gicv3_common.h173 uint32_t gicr_nsacr;

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