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/dports/multimedia/libva-intel-driver/intel-vaapi-driver-2.4.1/src/
H A Di965_pciids.h63 CHIPSET(0x040B, hsw, hsw_gt1, "Intel(R) Haswell")
64 CHIPSET(0x041B, hsw, hsw_gt2, "Intel(R) Haswell")
65 CHIPSET(0x042B, hsw, hsw_gt3, "Intel(R) Haswell")
66 CHIPSET(0x040E, hsw, hsw_gt1, "Intel(R) Haswell")
67 CHIPSET(0x041E, hsw, hsw_gt2, "Intel(R) Haswell")
68 CHIPSET(0x042E, hsw, hsw_gt3, "Intel(R) Haswell")
78 CHIPSET(0x0C0B, hsw, hsw_gt1, "Intel(R) Haswell")
79 CHIPSET(0x0C1B, hsw, hsw_gt2, "Intel(R) Haswell")
80 CHIPSET(0x0C2B, hsw, hsw_gt3, "Intel(R) Haswell")
81 CHIPSET(0x0C0E, hsw, hsw_gt1, "Intel(R) Haswell")
[all …]
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/crocus/ci/
H A Dtraces-crocus.yml9 - device: crocus-hsw
16 - device: crocus-hsw
22 - device: crocus-hsw
29 - device: crocus-hsw
44 - device: crocus-hsw
49 - device: crocus-hsw
56 - device: crocus-hsw
63 - device: crocus-hsw
70 - device: crocus-hsw
76 - device: crocus-hsw
[all …]
H A Dgitlab-ci.yml14 .anholt-hsw-test:
20 - anholt-hsw
22 GPU_VERSION: crocus-hsw
32 crocus-hsw-deqp:
34 - .anholt-hsw-test
37 DEQP_SUITE: crocus-hsw
57 crocus-hsw-piglit:
59 - .anholt-hsw-test
72 crocus-hsw-traces:
74 - .anholt-hsw-test
[all …]
/dports/net-p2p/bitmark-recorder/bitmarkd-0.13.3/debian/
H A Dchangelog5 -- Christopher Hall <hsw@bitmark.com> Tue, 13 Jul 2021 08:13:18 +0000
11 -- Christopher Hall <hsw@bitmark.com> Mon, 31 May 2021 07:52:14 +0000
17 -- Christopher Hall <hsw@bitmark.com> Tue, 04 May 2021 06:32:59 +0000
24 -- Christopher Hall <hsw@bitmark.com> Wed, 27 May 2020 06:53:51 +0000
33 -- Christopher Hall <hsw@bitmark.com> Wed, 22 Apr 2020 08:22:40 +0000
54 -- Christopher Hall <hsw@bitmark.com> Tue, 21 Apr 2020 02:22:36 +0000
61 -- Christopher Hall <hsw@bitmark.com> Wed, 15 Apr 2020 08:14:59 +0000
71 -- Christopher Hall <hsw@bitmark.com> Thu, 09 Apr 2020 03:03:12 +0000
80 -- Christopher Hall <hsw@bitmark.com> Thu, 26 Mar 2020 04:11:46 +0000
86 -- Christopher Hall <hsw@bitmark.com> Mon, 23 Mar 2020 02:00:03 +0000
[all …]
/dports/net-p2p/bitmark-cli/bitmarkd-0.13.3/debian/
H A Dchangelog5 -- Christopher Hall <hsw@bitmark.com> Tue, 13 Jul 2021 08:13:18 +0000
11 -- Christopher Hall <hsw@bitmark.com> Mon, 31 May 2021 07:52:14 +0000
17 -- Christopher Hall <hsw@bitmark.com> Tue, 04 May 2021 06:32:59 +0000
24 -- Christopher Hall <hsw@bitmark.com> Wed, 27 May 2020 06:53:51 +0000
33 -- Christopher Hall <hsw@bitmark.com> Wed, 22 Apr 2020 08:22:40 +0000
54 -- Christopher Hall <hsw@bitmark.com> Tue, 21 Apr 2020 02:22:36 +0000
61 -- Christopher Hall <hsw@bitmark.com> Wed, 15 Apr 2020 08:14:59 +0000
71 -- Christopher Hall <hsw@bitmark.com> Thu, 09 Apr 2020 03:03:12 +0000
80 -- Christopher Hall <hsw@bitmark.com> Thu, 26 Mar 2020 04:11:46 +0000
86 -- Christopher Hall <hsw@bitmark.com> Mon, 23 Mar 2020 02:00:03 +0000
[all …]
/dports/net-p2p/bitmark/bitmarkd-0.13.3/debian/
H A Dchangelog5 -- Christopher Hall <hsw@bitmark.com> Tue, 13 Jul 2021 08:13:18 +0000
11 -- Christopher Hall <hsw@bitmark.com> Mon, 31 May 2021 07:52:14 +0000
17 -- Christopher Hall <hsw@bitmark.com> Tue, 04 May 2021 06:32:59 +0000
24 -- Christopher Hall <hsw@bitmark.com> Wed, 27 May 2020 06:53:51 +0000
33 -- Christopher Hall <hsw@bitmark.com> Wed, 22 Apr 2020 08:22:40 +0000
54 -- Christopher Hall <hsw@bitmark.com> Tue, 21 Apr 2020 02:22:36 +0000
61 -- Christopher Hall <hsw@bitmark.com> Wed, 15 Apr 2020 08:14:59 +0000
71 -- Christopher Hall <hsw@bitmark.com> Thu, 09 Apr 2020 03:03:12 +0000
80 -- Christopher Hall <hsw@bitmark.com> Thu, 26 Mar 2020 04:11:46 +0000
86 -- Christopher Hall <hsw@bitmark.com> Mon, 23 Mar 2020 02:00:03 +0000
[all …]
/dports/net-p2p/bitmark-daemon/bitmarkd-0.13.3/debian/
H A Dchangelog5 -- Christopher Hall <hsw@bitmark.com> Tue, 13 Jul 2021 08:13:18 +0000
11 -- Christopher Hall <hsw@bitmark.com> Mon, 31 May 2021 07:52:14 +0000
17 -- Christopher Hall <hsw@bitmark.com> Tue, 04 May 2021 06:32:59 +0000
24 -- Christopher Hall <hsw@bitmark.com> Wed, 27 May 2020 06:53:51 +0000
33 -- Christopher Hall <hsw@bitmark.com> Wed, 22 Apr 2020 08:22:40 +0000
54 -- Christopher Hall <hsw@bitmark.com> Tue, 21 Apr 2020 02:22:36 +0000
61 -- Christopher Hall <hsw@bitmark.com> Wed, 15 Apr 2020 08:14:59 +0000
71 -- Christopher Hall <hsw@bitmark.com> Thu, 09 Apr 2020 03:03:12 +0000
80 -- Christopher Hall <hsw@bitmark.com> Thu, 26 Mar 2020 04:11:46 +0000
86 -- Christopher Hall <hsw@bitmark.com> Mon, 23 Mar 2020 02:00:03 +0000
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/i915/display/
H A Dintel_display_power.c3113 .hsw.has_vga = true,
3135 .hsw.has_vga = true,
3306 .hsw.has_fuses = true,
3336 .hsw.has_vga = true,
3337 .hsw.has_fuses = true,
3418 .hsw.has_vga = true,
3478 .hsw.has_vga = true,
3647 .hsw.has_vga = true,
3779 .hsw.has_vga = true,
4097 .hsw.has_vga = true,
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/i915/display/
H A Dintel_display_power.c3113 .hsw.has_vga = true,
3135 .hsw.has_vga = true,
3306 .hsw.has_fuses = true,
3336 .hsw.has_vga = true,
3337 .hsw.has_fuses = true,
3418 .hsw.has_vga = true,
3478 .hsw.has_vga = true,
3647 .hsw.has_vga = true,
3779 .hsw.has_vga = true,
4097 .hsw.has_vga = true,
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/i915/display/
H A Dintel_display_power.c3113 .hsw.has_vga = true,
3135 .hsw.has_vga = true,
3306 .hsw.has_fuses = true,
3336 .hsw.has_vga = true,
3337 .hsw.has_fuses = true,
3418 .hsw.has_vga = true,
3478 .hsw.has_vga = true,
3647 .hsw.has_vga = true,
3779 .hsw.has_vga = true,
4097 .hsw.has_vga = true,
[all …]
/dports/games/spring/spring_98.0/cont/base/springcontent/LuaIntro/Addons/
H A Dmain.lua35 local hsw = 0.2
40 gl.Vertex(0.2-hsw, 0.2 )
41 gl.Vertex(0.2-hsw, 0.2+vsw)
57 gl.Vertex(0.8+hsw, 0.2+vsw)
58 gl.Vertex(0.8+hsw, 0.2)
64 gl.Vertex(0.8+hsw, 0.2)
65 gl.Vertex(0.8+hsw, 0.15)
73 gl.Vertex(0.8+hsw, 0.15-vsw)
74 gl.Vertex(0.8+hsw, 0.15)
96 gl.Vertex(0.2-hsw, 0.2)
[all …]
/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/third_party/skia/src/opts/
H A DSkOpts_hsw.cpp10 #define SK_OPTS_NS hsw
20 blit_row_color32 = hsw::blit_row_color32; in Init_hsw()
21 blit_row_s32a_opaque = hsw::blit_row_s32a_opaque; in Init_hsw()
23 S32_alpha_D32_filter_DX = hsw::S32_alpha_D32_filter_DX; in Init_hsw()
/dports/www/firefox-esr/firefox-91.8.0/gfx/skia/skia/src/opts/
H A DSkOpts_hsw.cpp13 namespace hsw { namespace
102 #define SK_OPTS_NS hsw
115 convolve_vertically = hsw::convolve_vertically; in Init_hsw()
117 blit_row_color32 = hsw::blit_row_color32; in Init_hsw()
118 blit_row_s32a_opaque = hsw::blit_row_s32a_opaque; in Init_hsw()
120 S32_alpha_D32_filter_DX = hsw::S32_alpha_D32_filter_DX; in Init_hsw()
/dports/lang/spidermonkey78/firefox-78.9.0/gfx/skia/skia/src/opts/
H A DSkOpts_hsw.cpp13 namespace hsw { namespace
102 #define SK_OPTS_NS hsw
115 convolve_vertically = hsw::convolve_vertically; in Init_hsw()
117 blit_row_color32 = hsw::blit_row_color32; in Init_hsw()
118 blit_row_s32a_opaque = hsw::blit_row_s32a_opaque; in Init_hsw()
120 S32_alpha_D32_filter_DX = hsw::S32_alpha_D32_filter_DX; in Init_hsw()
/dports/www/firefox/firefox-99.0/gfx/skia/skia/src/opts/
H A DSkOpts_hsw.cpp13 namespace hsw { namespace
102 #define SK_OPTS_NS hsw
115 convolve_vertically = hsw::convolve_vertically; in Init_hsw()
117 blit_row_color32 = hsw::blit_row_color32; in Init_hsw()
118 blit_row_s32a_opaque = hsw::blit_row_s32a_opaque; in Init_hsw()
120 S32_alpha_D32_filter_DX = hsw::S32_alpha_D32_filter_DX; in Init_hsw()
/dports/mail/thunderbird/thunderbird-91.8.0/gfx/skia/skia/src/opts/
H A DSkOpts_hsw.cpp13 namespace hsw { namespace
102 #define SK_OPTS_NS hsw
115 convolve_vertically = hsw::convolve_vertically; in Init_hsw()
117 blit_row_color32 = hsw::blit_row_color32; in Init_hsw()
118 blit_row_s32a_opaque = hsw::blit_row_s32a_opaque; in Init_hsw()
120 S32_alpha_D32_filter_DX = hsw::S32_alpha_D32_filter_DX; in Init_hsw()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/skia/src/opts/
H A DSkOpts_hsw.cpp10 #define SK_OPTS_NS hsw
21 blit_row_color32 = hsw::blit_row_color32; in Init_hsw()
22 blit_row_s32a_opaque = hsw::blit_row_s32a_opaque; in Init_hsw()
24 S32_alpha_D32_filter_DX = hsw::S32_alpha_D32_filter_DX; in Init_hsw()
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/ArmPlatformPkg/Include/Drivers/
H A DPL111Lcd.h61 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) … argument
115 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) argument
116 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/ArmPlatformPkg/Library/PL111Lcd/
H A DPL111Lcd.h64 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) … argument
118 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) argument
119 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/ArmPlatformPkg/Library/PL111Lcd/
H A DPL111Lcd.h64 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) … argument
118 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) argument
119 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/ArmPlatformPkg/Library/PL111Lcd/
H A DPL111Lcd.h64 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) … argument
118 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) argument
119 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/ArmPlatformPkg/Library/PL111Lcd/
H A DPL111Lcd.h64 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) … argument
118 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) argument
119 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/ArmPlatformPkg/Library/PL111Lcd/
H A DPL111Lcd.h64 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) … argument
118 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) argument
119 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/ArmPlatformPkg/Library/PL111Lcd/
H A DPL111Lcd.h64 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) … argument
118 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) argument
119 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/ArmPlatformPkg/Library/PL111Lcd/
H A DPL111Lcd.h64 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) … argument
118 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) argument
119 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)

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