1 /** @file PL111Lcd.h 2 3 Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> 4 SPDX-License-Identifier: BSD-2-Clause-Patent 5 6 **/ 7 8 #ifndef _PL111LCD_H__ 9 #define _PL111LCD_H__ 10 11 /********************************************************************** 12 * 13 * This header file contains all the bits of the PL111 that are 14 * platform independent. 15 * 16 **********************************************************************/ 17 18 // Controller Register Offsets 19 #define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) 20 #define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) 21 #define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) 22 #define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) 23 #define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) 24 #define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) 25 #define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) 26 #define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) 27 #define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) 28 #define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) 29 #define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) 30 #define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) 31 #define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) 32 #define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) 33 34 // Identification Register Offsets 35 #define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) 36 #define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) 37 #define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) 38 #define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) 39 #define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) 40 #define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) 41 #define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) 42 #define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) 43 44 #define PL111_CLCD_PERIPH_ID_0 0x11 45 #define PL111_CLCD_PERIPH_ID_1 0x11 46 #define PL111_CLCD_PERIPH_ID_2 0x04 47 #define PL111_CLCD_PERIPH_ID_3 0x00 48 #define PL111_CLCD_P_CELL_ID_0 0x0D 49 #define PL111_CLCD_P_CELL_ID_1 0xF0 50 #define PL111_CLCD_P_CELL_ID_2 0x05 51 #define PL111_CLCD_P_CELL_ID_3 0xB1 52 53 /**********************************************************************/ 54 55 // Register components (register bits) 56 57 // This should make life easier to program specific settings in the different registers 58 // by simplifying the setting up of the individual bits of each register 59 // and then assembling the final register value. 60 61 /**********************************************************************/ 62 63 // Register: PL111_REG_LCD_TIMING_0 64 #define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2)) 65 66 // Register: PL111_REG_LCD_TIMING_1 67 #define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) 68 69 // Register: PL111_REG_LCD_TIMING_2 70 #define PL111_BIT_SHIFT_PCD_HI 27 71 #define PL111_BIT_SHIFT_BCD 26 72 #define PL111_BIT_SHIFT_CPL 16 73 #define PL111_BIT_SHIFT_IOE 14 74 #define PL111_BIT_SHIFT_IPC 13 75 #define PL111_BIT_SHIFT_IHS 12 76 #define PL111_BIT_SHIFT_IVS 11 77 #define PL111_BIT_SHIFT_ACB 6 78 #define PL111_BIT_SHIFT_CLKSEL 5 79 #define PL111_BIT_SHIFT_PCD_LO 0 80 81 #define PL111_BCD (1 << 26) 82 #define PL111_IPC (1 << 13) 83 #define PL111_IHS (1 << 12) 84 #define PL111_IVS (1 << 11) 85 86 #define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) 87 88 // Register: PL111_REG_LCD_TIMING_3 89 #define PL111_BIT_SHIFT_LEE 16 90 #define PL111_BIT_SHIFT_LED 0 91 92 #define PL111_CTRL_WATERMARK (1 << 16) 93 #define PL111_CTRL_LCD_V_COMP (1 << 12) 94 #define PL111_CTRL_LCD_PWR (1 << 11) 95 #define PL111_CTRL_BEPO (1 << 10) 96 #define PL111_CTRL_BEBO (1 << 9) 97 #define PL111_CTRL_BGR (1 << 8) 98 #define PL111_CTRL_LCD_DUAL (1 << 7) 99 #define PL111_CTRL_LCD_MONO_8 (1 << 6) 100 #define PL111_CTRL_LCD_TFT (1 << 5) 101 #define PL111_CTRL_LCD_BW (1 << 4) 102 #define PL111_CTRL_LCD_1BPP (0 << 1) 103 #define PL111_CTRL_LCD_2BPP (1 << 1) 104 #define PL111_CTRL_LCD_4BPP (2 << 1) 105 #define PL111_CTRL_LCD_8BPP (3 << 1) 106 #define PL111_CTRL_LCD_16BPP (4 << 1) 107 #define PL111_CTRL_LCD_24BPP (5 << 1) 108 #define PL111_CTRL_LCD_16BPP_565 (6 << 1) 109 #define PL111_CTRL_LCD_12BPP_444 (7 << 1) 110 #define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) 111 #define PL111_CTRL_LCD_EN 1 112 113 /**********************************************************************/ 114 115 // Register: PL111_REG_LCD_TIMING_0 116 #define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) 117 #define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) 118 #define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) 119 #define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) 120 121 // Register: PL111_REG_LCD_TIMING_1 122 #define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) 123 #define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) 124 #define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) 125 #define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) 126 127 // Register: PL111_REG_LCD_TIMING_2 128 #define PL111_BIT_MASK_PCD_HI 0xF8000000 129 #define PL111_BIT_MASK_BCD 0x04000000 130 #define PL111_BIT_MASK_CPL 0x03FF0000 131 #define PL111_BIT_MASK_IOE 0x00004000 132 #define PL111_BIT_MASK_IPC 0x00002000 133 #define PL111_BIT_MASK_IHS 0x00001000 134 #define PL111_BIT_MASK_IVS 0x00000800 135 #define PL111_BIT_MASK_ACB 0x000007C0 136 #define PL111_BIT_MASK_CLKSEL 0x00000020 137 #define PL111_BIT_MASK_PCD_LO 0x0000001F 138 139 // Register: PL111_REG_LCD_TIMING_3 140 #define PL111_BIT_MASK_LEE 0x00010000 141 #define PL111_BIT_MASK_LED 0x0000007F 142 143 #endif /* _PL111LCD_H__ */ 144