/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc/arp_responder/ |
H A D | arp_responder.vhd | 33 m_axis_tdata : out std_logic_vector(63 downto 0); port 67 m_axis_tdata <= (others => 'X'); 72 m_axis_tdata(47 downto 0) <= src_mac_be; 79 m_axis_tdata(47 downto 32) <= X"0608"; 80 m_axis_tdata(63 downto 48) <= X"0100"; 84 m_axis_tdata(15 downto 0) <= X"0008"; --PTYPE 85 m_axis_tdata(23 downto 16) <= X"06"; --HLEN 86 m_axis_tdata(31 downto 24) <= X"04"; --PLEN 87 m_axis_tdata(47 downto 32) <= X"0200"; --OPER 99 m_axis_tdata(47 downto 0) <= sender_hw_addr_be; --THA [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc/ |
H A D | arm_deframer.v | 29 output reg [63:0] m_axis_tdata, port 68 m_axis_tdata = 64'b0; 77 m_axis_tdata = {s_axis_tdata[15:0], 48'b0}; 88 m_axis_tdata = {s_axis_tdata[15:0], holding_reg}; 98 m_axis_tdata = {16'b0, holding_reg}; 110 m_axis_tdata = 64'b0;
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H A D | cvita_to_axis.v | 17 output wire [63:0] m_axis_tdata, port 25 assign m_axis_tdata = {i_tdata[31:0], i_tdata[63:32]};
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/axi/ |
H A D | axis_upsizer.v | 39 output wire [(IN_DATA_W*RATIO)-1:0] m_axis_tdata, // Output stream tdata port 80 assign m_axis_tdata[(i*IN_DATA_W)+:IN_DATA_W] = s_axis_tdata; 83 assign m_axis_tdata[(i*IN_DATA_W)+:IN_DATA_W] = keep[i+1] ? cached_data[i] : s_axis_tdata; 95 assign m_axis_tdata = s_axis_tdata;
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H A D | axis_width_conv.v | 51 output wire [(OUT_WORDS*WORD_W)-1:0] m_axis_tdata, // Output stream tdata port 91 .o_tdata({m_axis_tlast, m_axis_tkeep, m_axis_tdata}), 96 assign {m_axis_tlast, m_axis_tkeep, m_axis_tdata} = {o_tlast, o_tkeep, o_tdata}; 172 .m_axis_tdata(fifo_i_tdata), .m_axis_tuser(up_keep_flat), .m_axis_tkeep(up_keep_keep), 228 .m_axis_tdata(o_tdata), .m_axis_tuser(o_tkeep),
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H A D | axis_downsizer.v | 40 output wire [OUT_DATA_W-1:0] m_axis_tdata, // Output stream tdata port 79 assign m_axis_tdata = in_data[select]; 88 assign m_axis_tdata = s_axis_tdata;
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H A D | axis_packet_flush.v | 50 output wire [WIDTH-1:0] m_axis_tdata, port 82 .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready), 86 … assign {m_axis_tlast, m_axis_tdata, m_axis_tvalid} = {o_pipe_tlast, o_pipe_tdata, o_pipe_tvalid};
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/fifo/axi_fifo_2clk/ |
H A D | axi_fifo_2clk_tb.sv | 18 wire [WIDTH-1:0] m_axis_tdata; net 38 .m_axis_tdata(m_axis_tdata), 113 assert(m_axis_tdata == i+1'b1) else $error("Incorrect FIFO data! (read)");
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/crossbar/ |
H A D | axis_ctrl_crossbar_nxn.v | 49 output wire [(NPORTS*WIDTH)-1:0] m_axis_tdata, port 94 .m_axis_tdata (o_tdata), 107 assign m_axis_tdata = o_tdata[(NPORTS*WIDTH)-1:0]; 122 .m_axis_tdata (i_tdata[(i*WIDTH)+:WIDTH]),
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H A D | axis_port_terminator.v | 22 output wire [DATA_W-1:0] m_axis_tdata, // Output data port 31 assign m_axis_tdata = {DATA_W{1'b0}};
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H A D | mesh_2d_dor_router_single_sw.v | 267 .m_axis_tdata (wst_i_tdata), 286 .m_axis_tdata (est_i_tdata), 305 .m_axis_tdata (nor_i_tdata), 324 .m_axis_tdata (sou_i_tdata), 389 ….m_axis_tdata ({m_axis_sou_tdata, m_axis_nor_tdata, m_axis_est_tdata, m_axis_wst_tdata, m_axi…
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H A D | chdr_crossbar_nxn.v | 65 output wire [(CHDR_W*NPORTS)-1:0] m_axis_tdata, port 280 .m_axis_tdata (swo_tdata [n] ), 350 .m_axis_tdata (m_axis_tdata [(n*CHDR_W)+:CHDR_W]), 371 .o_tdata (m_axis_tdata [(n*CHDR_W)+:CHDR_W]),
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H A D | axis_ingress_vc_buff.v | 25 output wire [WIDTH-1:0] m_axis_tdata, port 109 .o_tdata (m_axis_tdata ), 168 .o_tdata ({m_axis_tlast, m_axis_tdata}),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
H A D | datapath_gatekeeper.v | 27 output wire [WIDTH-1:0] m_axis_tdata, port 58 .m_axis_tdata(m_axis_tdata), .m_axis_tlast(m_axis_tlast),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/crossbar/synth/ |
H A D | axis_ctrl_crossbar_nxn_top.v.in | 18 (* dont_touch = "true"*) wire [(DWIDTH*NPORTS)-1:0] s_axis_tdata , m_axis_tdata ; net 39 .m_axis_tdata (m_axis_tdata ),
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H A D | chdr_crossbar_nxn_top.v.in | 18 (* dont_touch = "true"*) wire [(DWIDTH*NPORTS)-1:0] s_axis_tdata , m_axis_tdata ; net 43 .m_axis_tdata (m_axis_tdata),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
H A D | n3xx_mgt_io_core.v | 47 output [63:0] m_axis_tdata, port 124 .m_axis_tdata ({c2mac_tuser, c2mac_tdata}), 326 .rx_tdata(m_axis_tdata), 425 .rx_tdata(m_axis_tdata), 498 .m_axis_tdata(p2m_tdata), 545 .m_axis_tdata(m_axis_tdata), 629 assign m_axis_tdata = 64'h0;
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
H A D | x300_sfpp_io_core.v | 44 output [63:0] m_axis_tdata, port 95 .m_axis_tdata ({c2mac_tuser, c2mac_tdata}), 174 .rx_tdata(m_axis_tdata), 253 .rx_tdata(m_axis_tdata), 320 .m_axis_tdata(o_tdata), 375 .m_axis_tdata(m_axis_tdata),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
H A D | n3xx_mgt_io_core.v | 50 output [63:0] m_axis_tdata, port 137 .m_axis_tdata ({c2mac_tuser, c2mac_tdata}), 379 .rx_tdata(m_axis_tdata), 516 .rx_tdata(m_axis_tdata), 593 .m_axis_tdata(p2m_tdata), 643 .m_axis_tdata(p2m_tdata), 694 .m_axis_tdata(m_axis_tdata), 785 assign m_axis_tdata = 64'h0;
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/ |
H A D | rfnoc_fir_filter_core.v | 92 output wire [DATA_W-1:0] m_axis_tdata, port 187 .m_axis_data_tdata (m_axis_tdata[2*OUT_WIDTH-1:OUT_WIDTH]), 218 .m_axis_data_tdata (m_axis_tdata[OUT_WIDTH-1:0]),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/core/ |
H A D | chdr_data_swapper.v | 44 output wire [CHDR_W-1:0] m_axis_tdata, port 199 .m_axis_tdata (out_swap_tdata_pre), 220 .o_tdata ({m_axis_tlast, m_axis_tdata} ),
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/packet_proc/arp_responder/test/ |
H A D | arp_responder_test.vhd | 31 signal m_axis_tdata : std_logic_vector(63 downto 0); signal 150 if (m_axis_tdata /= ARP_REPLY_VECTOR(64*i+63 downto 64*i)) then 178 m_axis_tdata => m_axis_tdata,
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge_interface/ |
H A D | axi64_to_xge64.v | 26 output [63:0] m_axis_tdata, port 82 assign m_axis_tdata[63:0] = {s_axis_tdata[47:0], saved};
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/utils/ |
H A D | chdr_trim_payload.v | 31 output wire [CHDR_W-1:0] m_axis_tdata, port 89 assign m_axis_tdata = s_axis_tdata;
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H A D | chdr_pad_packet.v | 32 output wire [CHDR_W-1:0] m_axis_tdata, port 99 assign m_axis_tdata = s_axis_tdata;
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