Home
last modified time | relevance | path

Searched refs:m_ctrlport_req_wr (Results 1 – 25 of 64) sorted by relevance

123

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/utils/
H A Dctrlport_gate.v37 output reg m_ctrlport_req_wr, port
56 m_ctrlport_req_wr <= 1'b0;
61 m_ctrlport_req_wr <= s_ctrlport_req_wr;
77 if (m_ctrlport_req_rd || m_ctrlport_req_wr) begin
80 m_ctrlport_req_wr <= 1'b0;
H A Dctrlport_splitter.v51 output wire [ NUM_SLAVES-1:0] m_ctrlport_req_wr, port
66 assign m_ctrlport_req_wr = s_ctrlport_req_wr;
88 assign m_ctrlport_req_wr[i] = s_ctrlport_req_wr;
H A Dctrlport_combiner.v56 output reg m_ctrlport_req_wr, port
222 m_ctrlport_req_wr <= 1'b0;
229 m_ctrlport_req_wr <= req_wr [slave_sel];
240 m_ctrlport_req_wr <= 1'b0;
H A Dctrlport_decoder_param.v74 output reg [ NUM_SLAVES-1:0] m_ctrlport_req_wr = 0, port
116 m_ctrlport_req_wr[i] <= 1'b0;
120 m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & dec_mask[i];
H A Dctrlport_decoder.v58 output reg [ NUM_SLAVES-1:0] m_ctrlport_req_wr = 0, port
98 m_ctrlport_req_wr[i] <= 1'b0;
102 m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & decoder[i];
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/
H A Drfnoc_block_siggen.v75 wire m_ctrlport_req_wr; net
145 .m_ctrlport_req_wr (m_ctrlport_req_wr),
189 .s_ctrlport_req_wr (m_ctrlport_req_wr),
199 .m_ctrlport_req_wr (ctrlport_req_wr),
H A Dnoc_shell_siggen.v77 output wire m_ctrlport_req_wr, port
178 .m_ctrlport_req_wr (m_ctrlport_req_wr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/
H A Dradio_core.v43 output wire m_ctrlport_req_wr, port
149 .m_ctrlport_req_wr ({ctrlport_general_req_wr,
218 .m_ctrlport_req_wr (m_ctrlport_req_wr),
309 .m_ctrlport_req_wr (ctrlport_err_tx_req_wr),
348 .m_ctrlport_req_wr (ctrlport_err_rx_req_wr),
H A Drfnoc_block_radio.v80 output wire m_ctrlport_req_wr, port
200 .m_ctrlport_req_wr (ctrlport_reg_req_wr),
295 .m_ctrlport_req_wr ({m_ctrlport_req_wr,
357 .m_ctrlport_req_wr (ctrlport_radios_req_wr),
408 .m_ctrlport_req_wr (ctrlport_err_req_wr),
487 .m_ctrlport_req_wr (ctrlport_err_radio_req_wr[i]),
H A Dradio_tx_core.v54 output reg m_ctrlport_req_wr = 1'b0, port
377 m_ctrlport_req_wr <= 1'b0;
381 m_ctrlport_req_wr <= 1'b0;
388 m_ctrlport_req_wr <= 1'b1;
H A Dradio_rx_core.v54 output reg m_ctrlport_req_wr = 1'b0, port
343 m_ctrlport_req_wr <= 1'b0;
350 m_ctrlport_req_wr <= 1'b0;
452 m_ctrlport_req_wr <= 1'b1;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/
H A Daxil_ctrlport_master.v50 output reg m_ctrlport_req_wr, port
114 m_ctrlport_req_wr <= 1'b0;
199 m_ctrlport_req_wr <= 1'b1;
210 m_ctrlport_req_wr <= 1'b0;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/
H A Drfnoc_block_moving_avg.v72 wire m_ctrlport_req_wr; net
160 .m_ctrlport_req_wr (m_ctrlport_req_wr),
225 .s_ctrlport_req_wr (m_ctrlport_req_wr),
235 .m_ctrlport_req_wr (ctrlport_req_wr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/
H A Drfnoc_block_window.v78 wire m_ctrlport_req_wr; net
163 .m_ctrlport_req_wr (m_ctrlport_req_wr),
228 .s_ctrlport_req_wr (m_ctrlport_req_wr),
238 .m_ctrlport_req_wr (ctrlport_req_wr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/
H A Drfnoc_block_fir_filter.v188 .m_ctrlport_req_wr (ctrlport_reg_req_wr),
234 wire [ NUM_PORTS-1:0] m_ctrlport_req_wr; net
258 .m_ctrlport_req_wr (m_ctrlport_req_wr),
289 .s_ctrlport_req_wr (m_ctrlport_req_wr[i]),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/examples/rfnoc-example/fpga/rfnoc_block_gain/
H A Drfnoc_block_gain.v68 wire m_ctrlport_req_wr; net
150 .m_ctrlport_req_wr (m_ctrlport_req_wr),
233 if (m_ctrlport_req_wr) begin
H A Dnoc_shell_gain.v74 output wire m_ctrlport_req_wr, port
172 .m_ctrlport_req_wr (m_ctrlport_req_wr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_vector_iir/
H A Drfnoc_block_vector_iir.v84 wire m_ctrlport_req_wr; net
170 .m_ctrlport_req_wr (m_ctrlport_req_wr),
232 .s_ctrlport_req_wr (m_ctrlport_req_wr),
242 .m_ctrlport_req_wr (dec_ctrlport_req_wr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/
H A De31x_core.v171 wire m_ctrlport_req_wr; net
236 .m_ctrlport_req_wr (cp_req_wr_aclk),
277 .m_ctrlport_req_wr (cp_req_wr),
324 .m_ctrlport_req_wr ({ cp_tk_req_wr, cp_glob_req_wr }),
674 .m_ctrlport_req_wr (m_ctrlport_req_wr ),
711 .s_ctrlport_req_wr (m_ctrlport_req_wr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fosphor/
H A Drfnoc_block_fosphor.v84 wire m_ctrlport_req_wr; net
165 .m_ctrlport_req_wr (m_ctrlport_req_wr),
267 if (m_ctrlport_req_wr) begin
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/
H A Drfnoc_block_keep_one_in_n.v70 wire m_ctrlport_req_wr; net
145 .m_ctrlport_req_wr (m_ctrlport_req_wr),
189 .s_ctrlport_req_wr (m_ctrlport_req_wr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/
H A Drfnoc_block_switchboard.v88 wire m_ctrlport_req_wr; net
158 .m_ctrlport_req_wr (m_ctrlport_req_wr),
221 end else if (m_ctrlport_req_wr) begin
H A Dnoc_shell_switchboard.v76 output wire m_ctrlport_req_wr, port
160 .m_ctrlport_req_wr (m_ctrlport_req_wr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/utils/rfnoc_blocktool/templates/modules/
H A Dctrlport_connect_template.mako5 .m_ctrlport_req_wr (m_ctrlport_req_wr),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/
H A Drfnoc_block_axi_ram_fifo.v264 .m_ctrlport_req_wr (ctrlport_req_wr),
294 wire [ NUM_PORTS-1:0] m_ctrlport_req_wr; net
318 .m_ctrlport_req_wr (m_ctrlport_req_wr),
436 .s_ctrlport_req_wr (m_ctrlport_req_wr[i]),

123