| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| /dports/graphics/libosmesa/mesa-21.3.6/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| H A D | midgard.h | 254 midgard_reg_mode_8 = 0, enumerator
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| /dports/graphics/mesa-libs/mesa-21.3.6/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
447 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
533 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
846 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| /dports/graphics/mesa-dri/mesa-21.3.6/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| /dports/lang/clover/mesa-21.3.6/src/panfrost/midgard/ |
| H A D | disassemble.c | 136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
377 case midgard_reg_mode_8: in bits_for_mode()
444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()
530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()
841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
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| H A D | midgard_print_constant.c | 146 case midgard_reg_mode_8: in mir_print_constant_component()
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| H A D | midgard.h | 254 midgard_reg_mode_8 = 0, enumerator
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| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/panfrost/midgard/ |
| H A D | midgard.h | 223 midgard_reg_mode_8 = 0, enumerator
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| H A D | midgard_ops.c | 177 #define M8 midgard_reg_mode_8
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| H A D | midgard_print.c | 223 case midgard_reg_mode_8: in mir_print_constant_component()
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