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Searched refs:mmUVD_STATUS (Results 1 – 25 of 57) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
385 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start()
411 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v3_1_start()
456 status = RREG32(mmUVD_STATUS); in uvd_v3_1_stop()
499 WREG32(mmUVD_STATUS, 0); in uvd_v3_1_stop()
701 if (RREG32(mmUVD_STATUS) != 0) in uvd_v3_1_hw_fini()
H A Duvd_v4_2.c215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v4_2_hw_fini()
263 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
317 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start()
343 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
388 status = RREG32(mmUVD_STATUS); in uvd_v4_2_stop()
431 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
H A Duvd_v5_0.c213 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
362 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
388 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
450 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
H A Dvcn_v1_0.c235 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) in vcn_v1_0_hw_fini()
786 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
787 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
858 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_spg_mode()
892 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
893 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1149 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); in vcn_v1_0_stop_spg_mode()
1333 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
1341 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
385 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start()
411 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v3_1_start()
456 status = RREG32(mmUVD_STATUS); in uvd_v3_1_stop()
499 WREG32(mmUVD_STATUS, 0); in uvd_v3_1_stop()
701 if (RREG32(mmUVD_STATUS) != 0) in uvd_v3_1_hw_fini()
H A Duvd_v4_2.c215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v4_2_hw_fini()
263 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
317 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start()
343 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
388 status = RREG32(mmUVD_STATUS); in uvd_v4_2_stop()
431 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
H A Duvd_v5_0.c213 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
362 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
388 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
450 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
H A Dvcn_v1_0.c235 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) in vcn_v1_0_hw_fini()
786 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
787 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
858 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_spg_mode()
892 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
893 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1149 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); in vcn_v1_0_stop_spg_mode()
1333 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
1341 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v4_2_hw_fini()
263 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
317 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start()
343 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
388 status = RREG32(mmUVD_STATUS); in uvd_v4_2_stop()
431 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
H A Duvd_v3_1.c331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
385 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start()
411 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v3_1_start()
456 status = RREG32(mmUVD_STATUS); in uvd_v3_1_stop()
499 WREG32(mmUVD_STATUS, 0); in uvd_v3_1_stop()
701 if (RREG32(mmUVD_STATUS) != 0) in uvd_v3_1_hw_fini()
H A Duvd_v5_0.c213 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
362 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
388 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
450 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
H A Dvcn_v1_0.c235 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) in vcn_v1_0_hw_fini()
786 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
787 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
858 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_spg_mode()
892 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
893 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1149 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); in vcn_v1_0_stop_spg_mode()
1333 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
1341 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h76 #define mmUVD_STATUS 0x3daf macro
H A Duvd_4_0_d.h84 #define mmUVD_STATUS 0x3DAF macro
H A Duvd_3_1_d.h78 #define mmUVD_STATUS 0x3daf macro
H A Duvd_5_0_d.h82 #define mmUVD_STATUS 0x3daf macro
H A Duvd_6_0_d.h98 #define mmUVD_STATUS 0x3daf macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h76 #define mmUVD_STATUS 0x3daf macro
H A Duvd_4_0_d.h84 #define mmUVD_STATUS 0x3DAF macro
H A Duvd_3_1_d.h78 #define mmUVD_STATUS 0x3daf macro
H A Duvd_5_0_d.h82 #define mmUVD_STATUS 0x3daf macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h84 #define mmUVD_STATUS 0x3DAF macro
H A Duvd_4_2_d.h76 #define mmUVD_STATUS 0x3daf macro
H A Duvd_3_1_d.h78 #define mmUVD_STATUS 0x3daf macro
H A Duvd_5_0_d.h82 #define mmUVD_STATUS 0x3daf macro

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