1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_vcn.h"
28 #include "amdgpu_pm.h"
29 #include "soc15.h"
30 #include "soc15d.h"
31 #include "soc15_common.h"
32
33 #include "vcn/vcn_1_0_offset.h"
34 #include "vcn/vcn_1_0_sh_mask.h"
35 #include "mmhub/mmhub_9_1_offset.h"
36 #include "mmhub/mmhub_9_1_sh_mask.h"
37
38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
39 #include "jpeg_v1_0.h"
40 #include "vcn_v1_0.h"
41
42 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab
43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1
44 #define mmUVD_REG_XX_MASK_1_0 0x05ac
45 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1
46
47 static int vcn_v1_0_stop(struct amdgpu_device *adev);
48 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
49 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
50 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
52 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
53 int inst_idx, struct dpg_pause_state *new_state);
54
55 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
56 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
57
58 /**
59 * vcn_v1_0_early_init - set function pointers
60 *
61 * @handle: amdgpu_device pointer
62 *
63 * Set ring and irq function pointers
64 */
vcn_v1_0_early_init(void * handle)65 static int vcn_v1_0_early_init(void *handle)
66 {
67 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
68
69 adev->vcn.num_vcn_inst = 1;
70 adev->vcn.num_enc_rings = 2;
71
72 vcn_v1_0_set_dec_ring_funcs(adev);
73 vcn_v1_0_set_enc_ring_funcs(adev);
74 vcn_v1_0_set_irq_funcs(adev);
75
76 jpeg_v1_0_early_init(handle);
77
78 return 0;
79 }
80
81 /**
82 * vcn_v1_0_sw_init - sw init for VCN block
83 *
84 * @handle: amdgpu_device pointer
85 *
86 * Load firmware and sw initialization
87 */
vcn_v1_0_sw_init(void * handle)88 static int vcn_v1_0_sw_init(void *handle)
89 {
90 struct amdgpu_ring *ring;
91 int i, r;
92 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
93
94 /* VCN DEC TRAP */
95 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
96 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
97 if (r)
98 return r;
99
100 /* VCN ENC TRAP */
101 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
102 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
103 &adev->vcn.inst->irq);
104 if (r)
105 return r;
106 }
107
108 r = amdgpu_vcn_sw_init(adev);
109 if (r)
110 return r;
111
112 /* Override the work func */
113 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
114
115 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
116 const struct common_firmware_header *hdr;
117 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
118 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
119 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
120 adev->firmware.fw_size +=
121 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
122 DRM_INFO("PSP loading VCN firmware\n");
123 }
124
125 r = amdgpu_vcn_resume(adev);
126 if (r)
127 return r;
128
129 ring = &adev->vcn.inst->ring_dec;
130 sprintf(ring->name, "vcn_dec");
131 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
132 AMDGPU_RING_PRIO_DEFAULT, NULL);
133 if (r)
134 return r;
135
136 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
137 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
138 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
139 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
140 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
141 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
142 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
143 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
144 adev->vcn.internal.nop = adev->vcn.inst->external.nop =
145 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
146
147 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
148 ring = &adev->vcn.inst->ring_enc[i];
149 sprintf(ring->name, "vcn_enc%d", i);
150 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
151 AMDGPU_RING_PRIO_DEFAULT, NULL);
152 if (r)
153 return r;
154 }
155
156 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
157
158 r = jpeg_v1_0_sw_init(handle);
159
160 return r;
161 }
162
163 /**
164 * vcn_v1_0_sw_fini - sw fini for VCN block
165 *
166 * @handle: amdgpu_device pointer
167 *
168 * VCN suspend and free up sw allocation
169 */
vcn_v1_0_sw_fini(void * handle)170 static int vcn_v1_0_sw_fini(void *handle)
171 {
172 int r;
173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
174
175 r = amdgpu_vcn_suspend(adev);
176 if (r)
177 return r;
178
179 jpeg_v1_0_sw_fini(handle);
180
181 r = amdgpu_vcn_sw_fini(adev);
182
183 return r;
184 }
185
186 /**
187 * vcn_v1_0_hw_init - start and test VCN block
188 *
189 * @handle: amdgpu_device pointer
190 *
191 * Initialize the hardware, boot up the VCPU and do some testing
192 */
vcn_v1_0_hw_init(void * handle)193 static int vcn_v1_0_hw_init(void *handle)
194 {
195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
196 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
197 int i, r;
198
199 r = amdgpu_ring_test_helper(ring);
200 if (r)
201 goto done;
202
203 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
204 ring = &adev->vcn.inst->ring_enc[i];
205 r = amdgpu_ring_test_helper(ring);
206 if (r)
207 goto done;
208 }
209
210 ring = &adev->jpeg.inst->ring_dec;
211 r = amdgpu_ring_test_helper(ring);
212 if (r)
213 goto done;
214
215 done:
216 if (!r)
217 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
218 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
219
220 return r;
221 }
222
223 /**
224 * vcn_v1_0_hw_fini - stop the hardware block
225 *
226 * @handle: amdgpu_device pointer
227 *
228 * Stop the VCN block, mark ring as not ready any more
229 */
vcn_v1_0_hw_fini(void * handle)230 static int vcn_v1_0_hw_fini(void *handle)
231 {
232 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
233
234 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
235 RREG32_SOC15(VCN, 0, mmUVD_STATUS))
236 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
237
238 return 0;
239 }
240
241 /**
242 * vcn_v1_0_suspend - suspend VCN block
243 *
244 * @handle: amdgpu_device pointer
245 *
246 * HW fini and suspend VCN block
247 */
vcn_v1_0_suspend(void * handle)248 static int vcn_v1_0_suspend(void *handle)
249 {
250 int r;
251 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
252
253 r = vcn_v1_0_hw_fini(adev);
254 if (r)
255 return r;
256
257 r = amdgpu_vcn_suspend(adev);
258
259 return r;
260 }
261
262 /**
263 * vcn_v1_0_resume - resume VCN block
264 *
265 * @handle: amdgpu_device pointer
266 *
267 * Resume firmware and hw init VCN block
268 */
vcn_v1_0_resume(void * handle)269 static int vcn_v1_0_resume(void *handle)
270 {
271 int r;
272 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
273
274 r = amdgpu_vcn_resume(adev);
275 if (r)
276 return r;
277
278 r = vcn_v1_0_hw_init(adev);
279
280 return r;
281 }
282
283 /**
284 * vcn_v1_0_mc_resume_spg_mode - memory controller programming
285 *
286 * @adev: amdgpu_device pointer
287 *
288 * Let the VCN memory controller know it's offsets
289 */
vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device * adev)290 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
291 {
292 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
293 uint32_t offset;
294
295 /* cache window 0: fw */
296 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
297 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
298 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
299 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
300 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
301 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
302 offset = 0;
303 } else {
304 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
305 lower_32_bits(adev->vcn.inst->gpu_addr));
306 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
307 upper_32_bits(adev->vcn.inst->gpu_addr));
308 offset = size;
309 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
310 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
311 }
312
313 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
314
315 /* cache window 1: stack */
316 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
317 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
318 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
319 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
320 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
321 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
322
323 /* cache window 2: context */
324 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
325 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
326 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
327 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
328 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
329 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
330
331 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
332 adev->gfx.config.gb_addr_config);
333 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
334 adev->gfx.config.gb_addr_config);
335 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
336 adev->gfx.config.gb_addr_config);
337 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
338 adev->gfx.config.gb_addr_config);
339 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
340 adev->gfx.config.gb_addr_config);
341 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
342 adev->gfx.config.gb_addr_config);
343 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
344 adev->gfx.config.gb_addr_config);
345 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
346 adev->gfx.config.gb_addr_config);
347 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
348 adev->gfx.config.gb_addr_config);
349 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
350 adev->gfx.config.gb_addr_config);
351 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
352 adev->gfx.config.gb_addr_config);
353 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
354 adev->gfx.config.gb_addr_config);
355 }
356
vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device * adev)357 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
358 {
359 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
360 uint32_t offset;
361
362 /* cache window 0: fw */
363 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
364 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
365 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
366 0xFFFFFFFF, 0);
367 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
368 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
369 0xFFFFFFFF, 0);
370 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
371 0xFFFFFFFF, 0);
372 offset = 0;
373 } else {
374 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
375 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
376 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
377 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
378 offset = size;
379 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
380 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
381 }
382
383 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
384
385 /* cache window 1: stack */
386 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
387 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
388 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
389 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
390 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
391 0xFFFFFFFF, 0);
392 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
393 0xFFFFFFFF, 0);
394
395 /* cache window 2: context */
396 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
397 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
398 0xFFFFFFFF, 0);
399 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
400 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
401 0xFFFFFFFF, 0);
402 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
403 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
404 0xFFFFFFFF, 0);
405
406 /* VCN global tiling registers */
407 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
408 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
409 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
410 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
411 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
412 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
413 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
414 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
415 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
416 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
417 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
418 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
419 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
420 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
421 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
422 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
423 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
424 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
425 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
426 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
427 }
428
429 /**
430 * vcn_v1_0_disable_clock_gating - disable VCN clock gating
431 *
432 * @adev: amdgpu_device pointer
433 *
434 * Disable clock gating for VCN block
435 */
vcn_v1_0_disable_clock_gating(struct amdgpu_device * adev)436 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
437 {
438 uint32_t data;
439
440 /* JPEG disable CGC */
441 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
442
443 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
444 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
445 else
446 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
447
448 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
449 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
450 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
451
452 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
453 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
454 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
455
456 /* UVD disable CGC */
457 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
458 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
459 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
460 else
461 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
462
463 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
464 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
465 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
466
467 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
468 data &= ~(UVD_CGC_GATE__SYS_MASK
469 | UVD_CGC_GATE__UDEC_MASK
470 | UVD_CGC_GATE__MPEG2_MASK
471 | UVD_CGC_GATE__REGS_MASK
472 | UVD_CGC_GATE__RBC_MASK
473 | UVD_CGC_GATE__LMI_MC_MASK
474 | UVD_CGC_GATE__LMI_UMC_MASK
475 | UVD_CGC_GATE__IDCT_MASK
476 | UVD_CGC_GATE__MPRD_MASK
477 | UVD_CGC_GATE__MPC_MASK
478 | UVD_CGC_GATE__LBSI_MASK
479 | UVD_CGC_GATE__LRBBM_MASK
480 | UVD_CGC_GATE__UDEC_RE_MASK
481 | UVD_CGC_GATE__UDEC_CM_MASK
482 | UVD_CGC_GATE__UDEC_IT_MASK
483 | UVD_CGC_GATE__UDEC_DB_MASK
484 | UVD_CGC_GATE__UDEC_MP_MASK
485 | UVD_CGC_GATE__WCB_MASK
486 | UVD_CGC_GATE__VCPU_MASK
487 | UVD_CGC_GATE__SCPU_MASK);
488 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
489
490 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
491 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
492 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
493 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
494 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
495 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
496 | UVD_CGC_CTRL__SYS_MODE_MASK
497 | UVD_CGC_CTRL__UDEC_MODE_MASK
498 | UVD_CGC_CTRL__MPEG2_MODE_MASK
499 | UVD_CGC_CTRL__REGS_MODE_MASK
500 | UVD_CGC_CTRL__RBC_MODE_MASK
501 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
502 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
503 | UVD_CGC_CTRL__IDCT_MODE_MASK
504 | UVD_CGC_CTRL__MPRD_MODE_MASK
505 | UVD_CGC_CTRL__MPC_MODE_MASK
506 | UVD_CGC_CTRL__LBSI_MODE_MASK
507 | UVD_CGC_CTRL__LRBBM_MODE_MASK
508 | UVD_CGC_CTRL__WCB_MODE_MASK
509 | UVD_CGC_CTRL__VCPU_MODE_MASK
510 | UVD_CGC_CTRL__SCPU_MODE_MASK);
511 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
512
513 /* turn on */
514 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
515 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
516 | UVD_SUVD_CGC_GATE__SIT_MASK
517 | UVD_SUVD_CGC_GATE__SMP_MASK
518 | UVD_SUVD_CGC_GATE__SCM_MASK
519 | UVD_SUVD_CGC_GATE__SDB_MASK
520 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
521 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
522 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
523 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
524 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
525 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
526 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
527 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
528 | UVD_SUVD_CGC_GATE__SCLR_MASK
529 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
530 | UVD_SUVD_CGC_GATE__ENT_MASK
531 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
532 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
533 | UVD_SUVD_CGC_GATE__SITE_MASK
534 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
535 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
536 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
537 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
538 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
539 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
540
541 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
542 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
543 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
544 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
545 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
546 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
547 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
548 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
549 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
550 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
551 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
552 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
553 }
554
555 /**
556 * vcn_v1_0_enable_clock_gating - enable VCN clock gating
557 *
558 * @adev: amdgpu_device pointer
559 *
560 * Enable clock gating for VCN block
561 */
vcn_v1_0_enable_clock_gating(struct amdgpu_device * adev)562 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
563 {
564 uint32_t data = 0;
565
566 /* enable JPEG CGC */
567 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
568 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
569 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
570 else
571 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
572 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
573 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
574 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
575
576 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
577 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
578 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
579
580 /* enable UVD CGC */
581 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
582 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
583 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
584 else
585 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
586 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
587 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
588 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
589
590 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
591 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
592 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
593 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
594 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
595 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
596 | UVD_CGC_CTRL__SYS_MODE_MASK
597 | UVD_CGC_CTRL__UDEC_MODE_MASK
598 | UVD_CGC_CTRL__MPEG2_MODE_MASK
599 | UVD_CGC_CTRL__REGS_MODE_MASK
600 | UVD_CGC_CTRL__RBC_MODE_MASK
601 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
602 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
603 | UVD_CGC_CTRL__IDCT_MODE_MASK
604 | UVD_CGC_CTRL__MPRD_MODE_MASK
605 | UVD_CGC_CTRL__MPC_MODE_MASK
606 | UVD_CGC_CTRL__LBSI_MODE_MASK
607 | UVD_CGC_CTRL__LRBBM_MODE_MASK
608 | UVD_CGC_CTRL__WCB_MODE_MASK
609 | UVD_CGC_CTRL__VCPU_MODE_MASK
610 | UVD_CGC_CTRL__SCPU_MODE_MASK);
611 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
612
613 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
614 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
615 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
616 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
617 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
618 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
619 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
620 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
621 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
622 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
623 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
624 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
625 }
626
vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel)627 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
628 {
629 uint32_t reg_data = 0;
630
631 /* disable JPEG CGC */
632 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
633 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
634 else
635 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
636 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
637 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
638 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
639
640 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
641
642 /* enable sw clock gating control */
643 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
644 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
645 else
646 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
647 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
648 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
649 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
650 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
651 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
652 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
653 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
654 UVD_CGC_CTRL__SYS_MODE_MASK |
655 UVD_CGC_CTRL__UDEC_MODE_MASK |
656 UVD_CGC_CTRL__MPEG2_MODE_MASK |
657 UVD_CGC_CTRL__REGS_MODE_MASK |
658 UVD_CGC_CTRL__RBC_MODE_MASK |
659 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
660 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
661 UVD_CGC_CTRL__IDCT_MODE_MASK |
662 UVD_CGC_CTRL__MPRD_MODE_MASK |
663 UVD_CGC_CTRL__MPC_MODE_MASK |
664 UVD_CGC_CTRL__LBSI_MODE_MASK |
665 UVD_CGC_CTRL__LRBBM_MODE_MASK |
666 UVD_CGC_CTRL__WCB_MODE_MASK |
667 UVD_CGC_CTRL__VCPU_MODE_MASK |
668 UVD_CGC_CTRL__SCPU_MODE_MASK);
669 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
670
671 /* turn off clock gating */
672 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
673
674 /* turn on SUVD clock gating */
675 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
676
677 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
678 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
679 }
680
vcn_1_0_disable_static_power_gating(struct amdgpu_device * adev)681 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
682 {
683 uint32_t data = 0;
684
685 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
686 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
687 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
688 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
689 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
690 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
691 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
692 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
693 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
694 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
695 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
696 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
697
698 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
699 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
700 } else {
701 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
702 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
703 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
704 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
705 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
706 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
707 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
708 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
709 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
710 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
711 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
712 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
713 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF);
714 }
715
716 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
717
718 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
719 data &= ~0x103;
720 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
721 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
722
723 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
724 }
725
vcn_1_0_enable_static_power_gating(struct amdgpu_device * adev)726 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
727 {
728 uint32_t data = 0;
729
730 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
731 /* Before power off, this indicator has to be turned on */
732 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
733 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
734 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
735 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
736
737
738 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
739 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
740 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
741 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
742 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
743 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
744 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
745 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
746 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
747 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
748 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
749
750 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
751
752 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
753 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
754 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
755 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
756 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
757 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
758 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
759 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
760 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
761 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
762 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
763 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
764 }
765 }
766
767 /**
768 * vcn_v1_0_start - start VCN block
769 *
770 * @adev: amdgpu_device pointer
771 *
772 * Setup and start the VCN block
773 */
vcn_v1_0_start_spg_mode(struct amdgpu_device * adev)774 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
775 {
776 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
777 uint32_t rb_bufsz, tmp;
778 uint32_t lmi_swap_cntl;
779 int i, j, r;
780
781 /* disable byte swapping */
782 lmi_swap_cntl = 0;
783
784 vcn_1_0_disable_static_power_gating(adev);
785
786 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
787 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
788
789 /* disable clock gating */
790 vcn_v1_0_disable_clock_gating(adev);
791
792 /* disable interupt */
793 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
794 ~UVD_MASTINT_EN__VCPU_EN_MASK);
795
796 /* initialize VCN memory controller */
797 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
798 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
799 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
800 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
801 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
802 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
803
804 #ifdef __BIG_ENDIAN
805 /* swap (8 in 32) RB and IB */
806 lmi_swap_cntl = 0xa;
807 #endif
808 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
809
810 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
811 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
812 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
813 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
814
815 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
816 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
817 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
818 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
819 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
820
821 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
822 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
823 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
824 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
825 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
826
827 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
828 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
829 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
830 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
831
832 vcn_v1_0_mc_resume_spg_mode(adev);
833
834 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
835 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
836 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);
837
838 /* enable VCPU clock */
839 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
840
841 /* boot up the VCPU */
842 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
843 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
844
845 /* enable UMC */
846 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
847 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
848
849 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
850 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
851 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
852 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
853
854 for (i = 0; i < 10; ++i) {
855 uint32_t status;
856
857 for (j = 0; j < 100; ++j) {
858 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
859 if (status & UVD_STATUS__IDLE)
860 break;
861 mdelay(10);
862 }
863 r = 0;
864 if (status & UVD_STATUS__IDLE)
865 break;
866
867 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
868 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
869 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
870 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
871 mdelay(10);
872 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
873 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
874 mdelay(10);
875 r = -1;
876 }
877
878 if (r) {
879 DRM_ERROR("VCN decode not responding, giving up!!!\n");
880 return r;
881 }
882 /* enable master interrupt */
883 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
884 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
885
886 /* enable system interrupt for JRBC, TODO: move to set interrupt*/
887 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
888 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
889 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
890
891 /* clear the busy bit of UVD_STATUS */
892 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
893 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
894
895 /* force RBC into idle state */
896 rb_bufsz = order_base_2(ring->ring_size);
897 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
898 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
899 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
900 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
901 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
902 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
903
904 /* set the write pointer delay */
905 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
906
907 /* set the wb address */
908 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
909 (upper_32_bits(ring->gpu_addr) >> 2));
910
911 /* program the RB_BASE for ring buffer */
912 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
913 lower_32_bits(ring->gpu_addr));
914 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
915 upper_32_bits(ring->gpu_addr));
916
917 /* Initialize the ring buffer's read and write pointers */
918 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
919
920 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
921
922 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
923 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
924 lower_32_bits(ring->wptr));
925
926 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
927 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
928
929 ring = &adev->vcn.inst->ring_enc[0];
930 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
931 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
932 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
933 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
934 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
935
936 ring = &adev->vcn.inst->ring_enc[1];
937 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
938 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
939 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
940 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
941 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
942
943 jpeg_v1_0_start(adev, 0);
944
945 return 0;
946 }
947
vcn_v1_0_start_dpg_mode(struct amdgpu_device * adev)948 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
949 {
950 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
951 uint32_t rb_bufsz, tmp;
952 uint32_t lmi_swap_cntl;
953
954 /* disable byte swapping */
955 lmi_swap_cntl = 0;
956
957 vcn_1_0_enable_static_power_gating(adev);
958
959 /* enable dynamic power gating mode */
960 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
961 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
962 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
963 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
964
965 /* enable clock gating */
966 vcn_v1_0_clock_gating_dpg_mode(adev, 0);
967
968 /* enable VCPU clock */
969 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
970 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
971 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
972 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
973
974 /* disable interupt */
975 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
976 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
977
978 /* initialize VCN memory controller */
979 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
980 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
981 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
982 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
983 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
984 UVD_LMI_CTRL__REQ_MODE_MASK |
985 UVD_LMI_CTRL__CRC_RESET_MASK |
986 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
987 0x00100000L, 0xFFFFFFFF, 0);
988
989 #ifdef __BIG_ENDIAN
990 /* swap (8 in 32) RB and IB */
991 lmi_swap_cntl = 0xa;
992 #endif
993 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
994
995 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
996 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
997
998 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
999 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1000 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1001 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1002 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1003
1004 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
1005 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1006 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1007 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1008 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1009
1010 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
1011 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1012 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1013 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1014
1015 vcn_v1_0_mc_resume_dpg_mode(adev);
1016
1017 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1018 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1019
1020 /* boot up the VCPU */
1021 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1022
1023 /* enable UMC */
1024 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
1025 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1026 0xFFFFFFFF, 0);
1027
1028 /* enable master interrupt */
1029 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1030 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1031
1032 vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1033 /* setup mmUVD_LMI_CTRL */
1034 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1035 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1036 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1037 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1038 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1039 UVD_LMI_CTRL__REQ_MODE_MASK |
1040 UVD_LMI_CTRL__CRC_RESET_MASK |
1041 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1042 0x00100000L, 0xFFFFFFFF, 1);
1043
1044 tmp = adev->gfx.config.gb_addr_config;
1045 /* setup VCN global tiling registers */
1046 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1047 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1048
1049 /* enable System Interrupt for JRBC */
1050 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
1051 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1052
1053 /* force RBC into idle state */
1054 rb_bufsz = order_base_2(ring->ring_size);
1055 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1056 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1057 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1058 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1059 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1060 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1061
1062 /* set the write pointer delay */
1063 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1064
1065 /* set the wb address */
1066 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1067 (upper_32_bits(ring->gpu_addr) >> 2));
1068
1069 /* program the RB_BASE for ring buffer */
1070 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1071 lower_32_bits(ring->gpu_addr));
1072 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1073 upper_32_bits(ring->gpu_addr));
1074
1075 /* Initialize the ring buffer's read and write pointers */
1076 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1077
1078 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1079
1080 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1081 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1082 lower_32_bits(ring->wptr));
1083
1084 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1085 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1086
1087 jpeg_v1_0_start(adev, 1);
1088
1089 return 0;
1090 }
1091
vcn_v1_0_start(struct amdgpu_device * adev)1092 static int vcn_v1_0_start(struct amdgpu_device *adev)
1093 {
1094 int r;
1095
1096 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1097 r = vcn_v1_0_start_dpg_mode(adev);
1098 else
1099 r = vcn_v1_0_start_spg_mode(adev);
1100 return r;
1101 }
1102
1103 /**
1104 * vcn_v1_0_stop - stop VCN block
1105 *
1106 * @adev: amdgpu_device pointer
1107 *
1108 * stop the VCN block
1109 */
vcn_v1_0_stop_spg_mode(struct amdgpu_device * adev)1110 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1111 {
1112 int tmp;
1113
1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1115
1116 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1117 UVD_LMI_STATUS__READ_CLEAN_MASK |
1118 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1119 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1120 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1121
1122 /* stall UMC channel */
1123 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1124 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1125 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1126
1127 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1128 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1129 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1130
1131 /* disable VCPU clock */
1132 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1133 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1134
1135 /* reset LMI UMC/LMI */
1136 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1137 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1138 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1139
1140 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1141 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1142 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1143
1144 /* put VCPU into reset */
1145 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1146 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1147 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1148
1149 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1150
1151 vcn_v1_0_enable_clock_gating(adev);
1152 vcn_1_0_enable_static_power_gating(adev);
1153 return 0;
1154 }
1155
vcn_v1_0_stop_dpg_mode(struct amdgpu_device * adev)1156 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1157 {
1158 uint32_t tmp;
1159
1160 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1161 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1162 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1163 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1164
1165 /* wait for read ptr to be equal to write ptr */
1166 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1167 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1168
1169 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1170 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1171
1172 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1173 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
1174
1175 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1176 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1177
1178 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1179 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1180 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1181
1182 /* disable dynamic power gating mode */
1183 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1184 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1185
1186 return 0;
1187 }
1188
vcn_v1_0_stop(struct amdgpu_device * adev)1189 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1190 {
1191 int r;
1192
1193 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1194 r = vcn_v1_0_stop_dpg_mode(adev);
1195 else
1196 r = vcn_v1_0_stop_spg_mode(adev);
1197
1198 return r;
1199 }
1200
vcn_v1_0_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)1201 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
1202 int inst_idx, struct dpg_pause_state *new_state)
1203 {
1204 int ret_code;
1205 uint32_t reg_data = 0;
1206 uint32_t reg_data2 = 0;
1207 struct amdgpu_ring *ring;
1208
1209 /* pause/unpause if state is changed */
1210 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1211 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1212 adev->vcn.inst[inst_idx].pause_state.fw_based,
1213 adev->vcn.inst[inst_idx].pause_state.jpeg,
1214 new_state->fw_based, new_state->jpeg);
1215
1216 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1217 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1218
1219 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1220 ret_code = 0;
1221
1222 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
1223 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1224 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1225 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1226
1227 if (!ret_code) {
1228 /* pause DPG non-jpeg */
1229 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1230 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1231 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1232 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1233 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1234
1235 /* Restore */
1236 ring = &adev->vcn.inst->ring_enc[0];
1237 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1238 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1239 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1240 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1241 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1242
1243 ring = &adev->vcn.inst->ring_enc[1];
1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1245 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1246 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1247 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1248 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1249
1250 ring = &adev->vcn.inst->ring_dec;
1251 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1252 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1253 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1254 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1255 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1256 }
1257 } else {
1258 /* unpause dpg non-jpeg, no need to wait */
1259 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1260 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1261 }
1262 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1263 }
1264
1265 /* pause/unpause if state is changed */
1266 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
1267 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1268 adev->vcn.inst[inst_idx].pause_state.fw_based,
1269 adev->vcn.inst[inst_idx].pause_state.jpeg,
1270 new_state->fw_based, new_state->jpeg);
1271
1272 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1273 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1274
1275 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
1276 ret_code = 0;
1277
1278 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
1279 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1280 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1281 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1282
1283 if (!ret_code) {
1284 /* Make sure JPRG Snoop is disabled before sending the pause */
1285 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1286 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
1287 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
1288
1289 /* pause DPG jpeg */
1290 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1291 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1292 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1293 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
1294 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1295
1296 /* Restore */
1297 ring = &adev->jpeg.inst->ring_dec;
1298 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
1299 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1300 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
1301 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1302 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
1303 lower_32_bits(ring->gpu_addr));
1304 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
1305 upper_32_bits(ring->gpu_addr));
1306 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
1307 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
1308 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1309 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1310
1311 ring = &adev->vcn.inst->ring_dec;
1312 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1313 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1314 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1315 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1316 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1317 }
1318 } else {
1319 /* unpause dpg jpeg, no need to wait */
1320 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1321 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1322 }
1323 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
1324 }
1325
1326 return 0;
1327 }
1328
vcn_v1_0_is_idle(void * handle)1329 static bool vcn_v1_0_is_idle(void *handle)
1330 {
1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1332
1333 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1334 }
1335
vcn_v1_0_wait_for_idle(void * handle)1336 static int vcn_v1_0_wait_for_idle(void *handle)
1337 {
1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339 int ret;
1340
1341 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1342 UVD_STATUS__IDLE);
1343
1344 return ret;
1345 }
1346
vcn_v1_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1347 static int vcn_v1_0_set_clockgating_state(void *handle,
1348 enum amd_clockgating_state state)
1349 {
1350 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1351 bool enable = (state == AMD_CG_STATE_GATE);
1352
1353 if (enable) {
1354 /* wait for STATUS to clear */
1355 if (!vcn_v1_0_is_idle(handle))
1356 return -EBUSY;
1357 vcn_v1_0_enable_clock_gating(adev);
1358 } else {
1359 /* disable HW gating and enable Sw gating */
1360 vcn_v1_0_disable_clock_gating(adev);
1361 }
1362 return 0;
1363 }
1364
1365 /**
1366 * vcn_v1_0_dec_ring_get_rptr - get read pointer
1367 *
1368 * @ring: amdgpu_ring pointer
1369 *
1370 * Returns the current hardware read pointer
1371 */
vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1372 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1373 {
1374 struct amdgpu_device *adev = ring->adev;
1375
1376 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1377 }
1378
1379 /**
1380 * vcn_v1_0_dec_ring_get_wptr - get write pointer
1381 *
1382 * @ring: amdgpu_ring pointer
1383 *
1384 * Returns the current hardware write pointer
1385 */
vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1386 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1387 {
1388 struct amdgpu_device *adev = ring->adev;
1389
1390 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1391 }
1392
1393 /**
1394 * vcn_v1_0_dec_ring_set_wptr - set write pointer
1395 *
1396 * @ring: amdgpu_ring pointer
1397 *
1398 * Commits the write pointer to the hardware
1399 */
vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1400 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1401 {
1402 struct amdgpu_device *adev = ring->adev;
1403
1404 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1405 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1406 lower_32_bits(ring->wptr) | 0x80000000);
1407
1408 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1409 }
1410
1411 /**
1412 * vcn_v1_0_dec_ring_insert_start - insert a start command
1413 *
1414 * @ring: amdgpu_ring pointer
1415 *
1416 * Write a start command to the ring.
1417 */
vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring * ring)1418 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1419 {
1420 struct amdgpu_device *adev = ring->adev;
1421
1422 amdgpu_ring_write(ring,
1423 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1424 amdgpu_ring_write(ring, 0);
1425 amdgpu_ring_write(ring,
1426 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1427 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1428 }
1429
1430 /**
1431 * vcn_v1_0_dec_ring_insert_end - insert a end command
1432 *
1433 * @ring: amdgpu_ring pointer
1434 *
1435 * Write a end command to the ring.
1436 */
vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring * ring)1437 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1438 {
1439 struct amdgpu_device *adev = ring->adev;
1440
1441 amdgpu_ring_write(ring,
1442 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1443 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1444 }
1445
1446 /**
1447 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1448 *
1449 * @ring: amdgpu_ring pointer
1450 * @addr: address
1451 * @seq: sequence number
1452 * @flags: fence related flags
1453 *
1454 * Write a fence and a trap command to the ring.
1455 */
vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1456 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1457 unsigned flags)
1458 {
1459 struct amdgpu_device *adev = ring->adev;
1460
1461 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1462
1463 amdgpu_ring_write(ring,
1464 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1465 amdgpu_ring_write(ring, seq);
1466 amdgpu_ring_write(ring,
1467 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1468 amdgpu_ring_write(ring, addr & 0xffffffff);
1469 amdgpu_ring_write(ring,
1470 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1471 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1472 amdgpu_ring_write(ring,
1473 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1474 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1475
1476 amdgpu_ring_write(ring,
1477 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1478 amdgpu_ring_write(ring, 0);
1479 amdgpu_ring_write(ring,
1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1481 amdgpu_ring_write(ring, 0);
1482 amdgpu_ring_write(ring,
1483 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1484 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1485 }
1486
1487 /**
1488 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1489 *
1490 * @ring: amdgpu_ring pointer
1491 * @job: job to retrieve vmid from
1492 * @ib: indirect buffer to execute
1493 * @flags: unused
1494 *
1495 * Write ring commands to execute the indirect buffer
1496 */
vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1497 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1498 struct amdgpu_job *job,
1499 struct amdgpu_ib *ib,
1500 uint32_t flags)
1501 {
1502 struct amdgpu_device *adev = ring->adev;
1503 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1504
1505 amdgpu_ring_write(ring,
1506 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1507 amdgpu_ring_write(ring, vmid);
1508
1509 amdgpu_ring_write(ring,
1510 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1511 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1512 amdgpu_ring_write(ring,
1513 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1514 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1515 amdgpu_ring_write(ring,
1516 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1517 amdgpu_ring_write(ring, ib->length_dw);
1518 }
1519
vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1520 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1521 uint32_t reg, uint32_t val,
1522 uint32_t mask)
1523 {
1524 struct amdgpu_device *adev = ring->adev;
1525
1526 amdgpu_ring_write(ring,
1527 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1528 amdgpu_ring_write(ring, reg << 2);
1529 amdgpu_ring_write(ring,
1530 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1531 amdgpu_ring_write(ring, val);
1532 amdgpu_ring_write(ring,
1533 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1534 amdgpu_ring_write(ring, mask);
1535 amdgpu_ring_write(ring,
1536 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1537 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1538 }
1539
vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1540 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1541 unsigned vmid, uint64_t pd_addr)
1542 {
1543 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1544 uint32_t data0, data1, mask;
1545
1546 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1547
1548 /* wait for register write */
1549 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1550 data1 = lower_32_bits(pd_addr);
1551 mask = 0xffffffff;
1552 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1553 }
1554
vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1555 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1556 uint32_t reg, uint32_t val)
1557 {
1558 struct amdgpu_device *adev = ring->adev;
1559
1560 amdgpu_ring_write(ring,
1561 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1562 amdgpu_ring_write(ring, reg << 2);
1563 amdgpu_ring_write(ring,
1564 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1565 amdgpu_ring_write(ring, val);
1566 amdgpu_ring_write(ring,
1567 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1568 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1569 }
1570
1571 /**
1572 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1573 *
1574 * @ring: amdgpu_ring pointer
1575 *
1576 * Returns the current hardware enc read pointer
1577 */
vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1578 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1579 {
1580 struct amdgpu_device *adev = ring->adev;
1581
1582 if (ring == &adev->vcn.inst->ring_enc[0])
1583 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1584 else
1585 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1586 }
1587
1588 /**
1589 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1590 *
1591 * @ring: amdgpu_ring pointer
1592 *
1593 * Returns the current hardware enc write pointer
1594 */
vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1595 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1596 {
1597 struct amdgpu_device *adev = ring->adev;
1598
1599 if (ring == &adev->vcn.inst->ring_enc[0])
1600 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1601 else
1602 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1603 }
1604
1605 /**
1606 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1607 *
1608 * @ring: amdgpu_ring pointer
1609 *
1610 * Commits the enc write pointer to the hardware
1611 */
vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1612 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1613 {
1614 struct amdgpu_device *adev = ring->adev;
1615
1616 if (ring == &adev->vcn.inst->ring_enc[0])
1617 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1618 lower_32_bits(ring->wptr));
1619 else
1620 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1621 lower_32_bits(ring->wptr));
1622 }
1623
1624 /**
1625 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1626 *
1627 * @ring: amdgpu_ring pointer
1628 * @addr: address
1629 * @seq: sequence number
1630 * @flags: fence related flags
1631 *
1632 * Write enc a fence and a trap command to the ring.
1633 */
vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1634 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1635 u64 seq, unsigned flags)
1636 {
1637 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1638
1639 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1640 amdgpu_ring_write(ring, addr);
1641 amdgpu_ring_write(ring, upper_32_bits(addr));
1642 amdgpu_ring_write(ring, seq);
1643 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1644 }
1645
vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring * ring)1646 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1647 {
1648 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1649 }
1650
1651 /**
1652 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1653 *
1654 * @ring: amdgpu_ring pointer
1655 * @job: job to retrive vmid from
1656 * @ib: indirect buffer to execute
1657 * @flags: unused
1658 *
1659 * Write enc ring commands to execute the indirect buffer
1660 */
vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1661 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1662 struct amdgpu_job *job,
1663 struct amdgpu_ib *ib,
1664 uint32_t flags)
1665 {
1666 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1667
1668 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1669 amdgpu_ring_write(ring, vmid);
1670 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1671 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1672 amdgpu_ring_write(ring, ib->length_dw);
1673 }
1674
vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1675 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1676 uint32_t reg, uint32_t val,
1677 uint32_t mask)
1678 {
1679 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1680 amdgpu_ring_write(ring, reg << 2);
1681 amdgpu_ring_write(ring, mask);
1682 amdgpu_ring_write(ring, val);
1683 }
1684
vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1685 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1686 unsigned int vmid, uint64_t pd_addr)
1687 {
1688 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1689
1690 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1691
1692 /* wait for reg writes */
1693 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1694 vmid * hub->ctx_addr_distance,
1695 lower_32_bits(pd_addr), 0xffffffff);
1696 }
1697
vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1698 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1699 uint32_t reg, uint32_t val)
1700 {
1701 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1702 amdgpu_ring_write(ring, reg << 2);
1703 amdgpu_ring_write(ring, val);
1704 }
1705
vcn_v1_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1706 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1707 struct amdgpu_irq_src *source,
1708 unsigned type,
1709 enum amdgpu_interrupt_state state)
1710 {
1711 return 0;
1712 }
1713
vcn_v1_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1714 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1715 struct amdgpu_irq_src *source,
1716 struct amdgpu_iv_entry *entry)
1717 {
1718 DRM_DEBUG("IH: VCN TRAP\n");
1719
1720 switch (entry->src_id) {
1721 case 124:
1722 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1723 break;
1724 case 119:
1725 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1726 break;
1727 case 120:
1728 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1729 break;
1730 default:
1731 DRM_ERROR("Unhandled interrupt: %d %d\n",
1732 entry->src_id, entry->src_data[0]);
1733 break;
1734 }
1735
1736 return 0;
1737 }
1738
vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1739 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1740 {
1741 struct amdgpu_device *adev = ring->adev;
1742 int i;
1743
1744 WARN_ON(ring->wptr % 2 || count % 2);
1745
1746 for (i = 0; i < count / 2; i++) {
1747 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1748 amdgpu_ring_write(ring, 0);
1749 }
1750 }
1751
vcn_v1_0_set_powergating_state(void * handle,enum amd_powergating_state state)1752 static int vcn_v1_0_set_powergating_state(void *handle,
1753 enum amd_powergating_state state)
1754 {
1755 /* This doesn't actually powergate the VCN block.
1756 * That's done in the dpm code via the SMC. This
1757 * just re-inits the block as necessary. The actual
1758 * gating still happens in the dpm code. We should
1759 * revisit this when there is a cleaner line between
1760 * the smc and the hw blocks
1761 */
1762 int ret;
1763 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1764
1765 if(state == adev->vcn.cur_state)
1766 return 0;
1767
1768 if (state == AMD_PG_STATE_GATE)
1769 ret = vcn_v1_0_stop(adev);
1770 else
1771 ret = vcn_v1_0_start(adev);
1772
1773 if(!ret)
1774 adev->vcn.cur_state = state;
1775 return ret;
1776 }
1777
vcn_v1_0_idle_work_handler(struct work_struct * work)1778 static void vcn_v1_0_idle_work_handler(struct work_struct *work)
1779 {
1780 struct amdgpu_device *adev =
1781 container_of(work, struct amdgpu_device, vcn.idle_work.work);
1782 unsigned int fences = 0, i;
1783
1784 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1785 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1786
1787 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1788 struct dpg_pause_state new_state;
1789
1790 if (fences)
1791 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1792 else
1793 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1794
1795 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1796 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1797 else
1798 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1799
1800 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1801 }
1802
1803 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec);
1804 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
1805
1806 if (fences == 0) {
1807 amdgpu_gfx_off_ctrl(adev, true);
1808 if (adev->pm.dpm_enabled)
1809 amdgpu_dpm_enable_uvd(adev, false);
1810 else
1811 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1812 AMD_PG_STATE_GATE);
1813 } else {
1814 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1815 }
1816 }
1817
vcn_v1_0_ring_begin_use(struct amdgpu_ring * ring)1818 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
1819 {
1820 struct amdgpu_device *adev = ring->adev;
1821 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
1822
1823 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
1824
1825 if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec))
1826 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
1827
1828 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
1829
1830 }
1831
vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring * ring,bool set_clocks)1832 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
1833 {
1834 struct amdgpu_device *adev = ring->adev;
1835
1836 if (set_clocks) {
1837 amdgpu_gfx_off_ctrl(adev, false);
1838 if (adev->pm.dpm_enabled)
1839 amdgpu_dpm_enable_uvd(adev, true);
1840 else
1841 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1842 AMD_PG_STATE_UNGATE);
1843 }
1844
1845 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1846 struct dpg_pause_state new_state;
1847 unsigned int fences = 0, i;
1848
1849 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1850 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1851
1852 if (fences)
1853 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1854 else
1855 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1856
1857 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1858 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1859 else
1860 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1861
1862 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
1863 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1864 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
1865 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1866
1867 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1868 }
1869 }
1870
vcn_v1_0_ring_end_use(struct amdgpu_ring * ring)1871 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
1872 {
1873 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1874 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
1875 }
1876
1877 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
1878 .name = "vcn_v1_0",
1879 .early_init = vcn_v1_0_early_init,
1880 .late_init = NULL,
1881 .sw_init = vcn_v1_0_sw_init,
1882 .sw_fini = vcn_v1_0_sw_fini,
1883 .hw_init = vcn_v1_0_hw_init,
1884 .hw_fini = vcn_v1_0_hw_fini,
1885 .suspend = vcn_v1_0_suspend,
1886 .resume = vcn_v1_0_resume,
1887 .is_idle = vcn_v1_0_is_idle,
1888 .wait_for_idle = vcn_v1_0_wait_for_idle,
1889 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
1890 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
1891 .soft_reset = NULL /* vcn_v1_0_soft_reset */,
1892 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
1893 .set_clockgating_state = vcn_v1_0_set_clockgating_state,
1894 .set_powergating_state = vcn_v1_0_set_powergating_state,
1895 };
1896
1897 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
1898 .type = AMDGPU_RING_TYPE_VCN_DEC,
1899 .align_mask = 0xf,
1900 .support_64bit_ptrs = false,
1901 .no_user_fence = true,
1902 .vmhub = AMDGPU_MMHUB_0,
1903 .get_rptr = vcn_v1_0_dec_ring_get_rptr,
1904 .get_wptr = vcn_v1_0_dec_ring_get_wptr,
1905 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1906 .emit_frame_size =
1907 6 + 6 + /* hdp invalidate / flush */
1908 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1909 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1910 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
1911 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
1912 6,
1913 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
1914 .emit_ib = vcn_v1_0_dec_ring_emit_ib,
1915 .emit_fence = vcn_v1_0_dec_ring_emit_fence,
1916 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
1917 .test_ring = amdgpu_vcn_dec_ring_test_ring,
1918 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1919 .insert_nop = vcn_v1_0_dec_ring_insert_nop,
1920 .insert_start = vcn_v1_0_dec_ring_insert_start,
1921 .insert_end = vcn_v1_0_dec_ring_insert_end,
1922 .pad_ib = amdgpu_ring_generic_pad_ib,
1923 .begin_use = vcn_v1_0_ring_begin_use,
1924 .end_use = vcn_v1_0_ring_end_use,
1925 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
1926 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
1927 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1928 };
1929
1930 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
1931 .type = AMDGPU_RING_TYPE_VCN_ENC,
1932 .align_mask = 0x3f,
1933 .nop = VCN_ENC_CMD_NO_OP,
1934 .support_64bit_ptrs = false,
1935 .no_user_fence = true,
1936 .vmhub = AMDGPU_MMHUB_0,
1937 .get_rptr = vcn_v1_0_enc_ring_get_rptr,
1938 .get_wptr = vcn_v1_0_enc_ring_get_wptr,
1939 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
1940 .emit_frame_size =
1941 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1942 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1943 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
1944 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
1945 1, /* vcn_v1_0_enc_ring_insert_end */
1946 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
1947 .emit_ib = vcn_v1_0_enc_ring_emit_ib,
1948 .emit_fence = vcn_v1_0_enc_ring_emit_fence,
1949 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
1950 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1951 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1952 .insert_nop = amdgpu_ring_insert_nop,
1953 .insert_end = vcn_v1_0_enc_ring_insert_end,
1954 .pad_ib = amdgpu_ring_generic_pad_ib,
1955 .begin_use = vcn_v1_0_ring_begin_use,
1956 .end_use = vcn_v1_0_ring_end_use,
1957 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
1958 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
1959 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1960 };
1961
vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device * adev)1962 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1963 {
1964 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
1965 DRM_INFO("VCN decode is enabled in VM mode\n");
1966 }
1967
vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device * adev)1968 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1969 {
1970 int i;
1971
1972 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1973 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
1974
1975 DRM_INFO("VCN encode is enabled in VM mode\n");
1976 }
1977
1978 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
1979 .set = vcn_v1_0_set_interrupt_state,
1980 .process = vcn_v1_0_process_interrupt,
1981 };
1982
vcn_v1_0_set_irq_funcs(struct amdgpu_device * adev)1983 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
1984 {
1985 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
1986 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
1987 }
1988
1989 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
1990 {
1991 .type = AMD_IP_BLOCK_TYPE_VCN,
1992 .major = 1,
1993 .minor = 0,
1994 .rev = 0,
1995 .funcs = &vcn_v1_0_ip_funcs,
1996 };
1997