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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_interface_gen12.v11 for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block block
24 bar.foo.my_gen_block[0].baz = 1;
25 if (bar.foo.my_gen_block[0].baz) begin