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Searched refs:rb_stencil_cntl (Results 1 – 25 of 30) sorted by relevance

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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2262 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2528 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2534 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2554 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2560 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2568 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2574 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3706 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3783 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3796 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1210 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member
H A Dtu_pipeline.c2868 uint32_t rb_depth_cntl = 0, rb_stencil_cntl = 0; in tu_pipeline_builder_parse_depth_stencil() local
2904 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2915 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2930 tu_cs_emit(&cs, rb_stencil_cntl); in tu_pipeline_builder_parse_depth_stencil()
2932 pipeline->rb_stencil_cntl = rb_stencil_cntl; in tu_pipeline_builder_parse_depth_stencil()
/dports/graphics/mesa-libs/mesa-21.3.6/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2262 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2528 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2534 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2554 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2560 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2568 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2574 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3706 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3783 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3796 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1210 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member
H A Dtu_pipeline.c2868 uint32_t rb_depth_cntl = 0, rb_stencil_cntl = 0; in tu_pipeline_builder_parse_depth_stencil() local
2904 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2915 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2930 tu_cs_emit(&cs, rb_stencil_cntl); in tu_pipeline_builder_parse_depth_stencil()
2932 pipeline->rb_stencil_cntl = rb_stencil_cntl; in tu_pipeline_builder_parse_depth_stencil()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2262 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2528 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2534 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2554 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2560 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2568 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2574 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3706 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3783 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3796 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1210 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member
H A Dtu_pipeline.c2868 uint32_t rb_depth_cntl = 0, rb_stencil_cntl = 0; in tu_pipeline_builder_parse_depth_stencil() local
2904 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2915 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2930 tu_cs_emit(&cs, rb_stencil_cntl); in tu_pipeline_builder_parse_depth_stencil()
2932 pipeline->rb_stencil_cntl = rb_stencil_cntl; in tu_pipeline_builder_parse_depth_stencil()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2262 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2528 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2534 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2554 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2560 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2568 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2574 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3706 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3783 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3796 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1210 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member
H A Dtu_pipeline.c2868 uint32_t rb_depth_cntl = 0, rb_stencil_cntl = 0; in tu_pipeline_builder_parse_depth_stencil() local
2904 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2915 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2930 tu_cs_emit(&cs, rb_stencil_cntl); in tu_pipeline_builder_parse_depth_stencil()
2932 pipeline->rb_stencil_cntl = rb_stencil_cntl; in tu_pipeline_builder_parse_depth_stencil()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2262 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2528 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2534 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2554 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2560 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2568 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2574 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3706 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3783 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3796 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1210 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member
H A Dtu_pipeline.c2868 uint32_t rb_depth_cntl = 0, rb_stencil_cntl = 0; in tu_pipeline_builder_parse_depth_stencil() local
2904 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2915 rb_stencil_cntl |= in tu_pipeline_builder_parse_depth_stencil()
2930 tu_cs_emit(&cs, rb_stencil_cntl); in tu_pipeline_builder_parse_depth_stencil()
2932 pipeline->rb_stencil_cntl = rb_stencil_cntl; in tu_pipeline_builder_parse_depth_stencil()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2262 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2528 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2534 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2554 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2560 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2568 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2574 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3706 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3783 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3796 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1210 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member
/dports/graphics/libosmesa/mesa-21.3.6/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2262 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2528 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2534 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2554 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2560 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2568 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2574 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3706 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3783 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3796 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1210 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2389 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2657 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2663 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2683 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2689 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2697 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2703 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3632 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3704 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3717 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h1068 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1333 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member
/dports/graphics/mesa-dri/mesa-21.3.6/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2262 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2528 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2534 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2554 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2560 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2568 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2574 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3706 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3783 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3796 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1210 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member
/dports/lang/clover/mesa-21.3.6/src/freedreno/vulkan/
H A Dtu_cmd_buffer.c2262 UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL); in tu_CmdBindPipeline()
2528 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilTestEnableEXT()
2534 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilTestEnableEXT()
2554 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2560 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
2568 cmd->state.rb_stencil_cntl &= ~( in tu_CmdSetStencilOpEXT()
2574 cmd->state.rb_stencil_cntl |= in tu_CmdSetStencilOpEXT()
3706 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_calculate_lrz_state()
3783 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE; in tu6_writes_stencil()
3796 …(cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_… in tu6_writes_stencil()
[all …]
H A Dtu_private.h978 uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl; member
1210 uint32_t rb_stencil_cntl, rb_stencil_cntl_mask; member

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