| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/ |
| H A D | ext_fifo.v | 31 module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
42 input rdclk; port
52 .rclk(rdclk), .rdata(q),.raddr(read_addr) );
61 always @(posedge rdclk or posedge reset)
74 always @(posedge rdclk or posedge reset)
83 always @(posedge rdclk or posedge reset)
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| H A D | tx_buffer.v | 93 .rdclk ( txclk ),
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| H A D | rx_buffer.v | 99 .rdclk ( ~usbclk ),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/models/ |
| H A D | fifo_1c_4k.v | 3 module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
13 input rdclk; port
54 always @(posedge rdclk)
72 always @(posedge rdclk)
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| H A D | fifo_1c_2k.v | 3 module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
13 input rdclk; port
54 always @(posedge rdclk)
72 always @(posedge rdclk)
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| H A D | fifo.v | 3 module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
15 input rdclk; port
53 always @(posedge rdclk)
71 always @(posedge rdclk)
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| H A D | fifo_1c_1k.v | 3 module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
13 input rdclk; port
54 always @(posedge rdclk)
72 always @(posedge rdclk)
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| H A D | fifo_1k.v | 7 input rdclk, port
20 ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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| H A D | fifo_2k.v | 7 input rdclk, port
20 ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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| H A D | fifo_4k.v | 7 input rdclk, port
20 ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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| H A D | fifo_4k_18.v | 13 input rdclk, port
21 ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/ |
| H A D | fifo_4kx16_dc.v | 39 rdclk,
51 input rdclk; port
76 .rdclk (rdclk),
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| H A D | fifo_4k_18.v | 42 rdclk,
54 input rdclk; port
79 .rdclk (rdclk),
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| H A D | fifo_2k_bb.v | 35 rdclk,
47 input rdclk; port
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| H A D | fifo_4k_bb.v | 35 rdclk,
47 input rdclk; port
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| H A D | fifo_4kx16_dc_bb.v | 34 rdclk,
46 input rdclk; port
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| H A D | fifo_4kx16_dc_inst.v | 4 .rdclk ( rdclk_sig ),
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| H A D | fifo_2k.v | 3018 rdclk,
3030 input rdclk; port
3089 .clock(rdclk),
3095 .clock(rdclk),
3109 .clock1(rdclk),
3130 .clock(rdclk),
3136 .clock(rdclk),
3142 .clock(rdclk),
3223 rdclk,
3235 input rdclk; port
[all …]
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| H A D | fifo_4k.v | 3170 rdclk,
3182 input rdclk; port
3241 .clock(rdclk),
3247 .clock(rdclk),
3261 .clock1(rdclk),
3282 .clock(rdclk),
3288 .clock(rdclk),
3294 .clock(rdclk),
3375 rdclk,
3387 input rdclk; port
[all …]
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| H A D | fifo_4kx16_dc.bsf | 57 (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
58 (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
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| H A D | fifo_4kx16_dc.inc | 20 rdclk,
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| H A D | fifo_4kx16_dc.cmp | 21 rdclk : IN STD_LOGIC ;
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/inband_lib/ |
| H A D | rx_buffer_inband.v | 97 .rdclk ( ~usbclk ),
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| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_altera_lpm.v | 6058 rdclk,
6086 input rdclk; port
6258 .clock (rdclk),
6268 .clock (rdclk),
6288 .clock (rdclk),
6298 .clock (rdclk),
6324 .clock (rdclk),
6405 always @(posedge rdclk)
6442 always @(negedge rdclk)
6447 always @(posedge rdclk)
[all …]
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