| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/models/ |
| H A D | fifo_1c_2k.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
19 output [10:0] rdusedw; port
34 reg [10:0] rdusedw; register
73 rdusedw <= #1 wrptr - rdptr;
78 assign rdempty = (rdusedw == 0);
79 assign rdfull = (rdusedw == depth-1);
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| H A D | fifo_1c_1k.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
19 output [9:0] rdusedw; port
34 reg [9:0] rdusedw; register
73 rdusedw <= #1 wrptr - rdptr;
78 assign rdempty = (rdusedw == 0);
79 assign rdfull = (rdusedw == depth-1);
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| H A D | fifo.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
21 output reg [addr_bits-1:0] rdusedw; port
72 rdusedw <= #1 wrptr - rdptr;
77 assign rdempty = (rdusedw == 0);
78 assign rdfull = (rdusedw == depth-1);
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| H A D | fifo_1c_4k.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
19 output [7:0] rdusedw; port
34 reg [7:0] rdusedw; register
73 rdusedw <= #1 wrptr - rdptr;
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| H A D | fifo_1k.v | 13 output [9:0] rdusedw, port
21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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| H A D | fifo_2k.v | 13 output [10:0] rdusedw, port
21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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| H A D | fifo_4k.v | 13 output [11:0] rdusedw, port
21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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| H A D | fifo_4k_18.v | 16 output [11:0] rdusedw, port
22 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/ |
| H A D | fifo_4kx16_dc.v | 45 rdusedw,
57 output [11:0] rdusedw; port
70 wire [11:0] rdusedw = sub_wire4[11:0]; net
83 .rdusedw (sub_wire4)
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| H A D | fifo_4k_18.v | 48 rdusedw,
60 output [11:0] rdusedw; port
73 wire [11:0] rdusedw = sub_wire4[11:0]; net
86 .rdusedw (sub_wire4)
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| H A D | fifo_2k_bb.v | 40 rdusedw,
52 output [10:0] rdusedw; port
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| H A D | fifo_4k_bb.v | 40 rdusedw,
52 output [11:0] rdusedw; port
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| H A D | fifo_4kx16_dc_bb.v | 40 rdusedw,
52 output [11:0] rdusedw; port
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| H A D | fifo_4kx16_dc_inst.v | 10 .rdusedw ( rdusedw_sig ),
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| H A D | fifo_4kx16_dc.bsf | 99 (text "rdusedw[11..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
100 (text "rdusedw[11..0]" (rect 67 130 135 143)(font "Arial" (font_size 8)))
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| H A D | fifo_4kx16_dc.inc | 29 rdusedw[11..0],
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| H A D | fifo_4kx16_dc.cmp | 27 rdusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
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| H A D | fifo_2k.v | 3021 rdusedw,
3033 output [10:0] rdusedw; port
3207 rdusedw = wire_rdusedw_sub_result,
3228 rdusedw,
3240 output [10:0] rdusedw; port
3253 wire [10:0] rdusedw = sub_wire4[10:0]; net
3266 .rdusedw (sub_wire4));
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| H A D | fifo_4k.v | 3173 rdusedw,
3185 output [11:0] rdusedw; port
3359 rdusedw = wire_rdusedw_sub_result,
3380 rdusedw,
3392 output [11:0] rdusedw; port
3405 wire [11:0] rdusedw = sub_wire4[11:0]; net
3418 .rdusedw (sub_wire4));
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/inband_lib/ |
| H A D | rx_buffer_inband.v | 62 wire [11:0] rdusedw; net
103 .rdusedw ( rdusedw ),
107 assign have_pkt_rdy = (rdusedw >= 12'd256);
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/ |
| H A D | tx_buffer.v | 96 .rdusedw ( ),
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| H A D | rx_buffer.v | 102 .rdusedw ( rxfifolevel ),
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| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_altera_lpm.v | 6067 rdusedw,
6097 output [lpm_widthu-1:0] rdusedw; port
6472 assign rdusedw = w_rdusedw;
6504 rdusedw,
6537 output [lpm_widthu-1:0] rdusedw; port
6574 .rdusedw (w_rdusedw_a),
6595 assign rdusedw = w_rdusedw_a;
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