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/dports/net-mgmt/coovachilli/coova-chilli-1.0.12/www/
H A Dconfig.sh.in9 reg_mode=${reg_mode:-$HS_REG_MODE}
10 [ "$reg_mode" = "self" ] && register=1
11 [ "$reg_mode" = "tos" ] && tos=1
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
H A Ddisassemble.c129 midgard_reg_mode reg_mode) in validate_expand_mode() argument
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
137 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
142 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
404 midgard_reg_mode reg_mode, in print_vec_selectors_64() argument
436 midgard_reg_mode reg_mode, in print_vec_selectors() argument
440 assert(reg_mode != midgard_reg_mode_64); in print_vec_selectors()
[all …]
/dports/graphics/libosmesa/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
H A Ddisassemble.c129 midgard_reg_mode reg_mode) in validate_expand_mode() argument
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
137 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
142 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
404 midgard_reg_mode reg_mode, in print_vec_selectors_64() argument
436 midgard_reg_mode reg_mode, in print_vec_selectors() argument
440 assert(reg_mode != midgard_reg_mode_64); in print_vec_selectors()
[all …]
/dports/graphics/mesa-libs/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
H A Ddisassemble.c129 midgard_reg_mode reg_mode) in validate_expand_mode() argument
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
137 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
142 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
404 midgard_reg_mode reg_mode, in print_vec_selectors_64() argument
436 midgard_reg_mode reg_mode, in print_vec_selectors() argument
440 assert(reg_mode != midgard_reg_mode_64); in print_vec_selectors()
[all …]
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
H A Ddisassemble.c129 midgard_reg_mode reg_mode) in validate_expand_mode() argument
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
137 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
142 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
404 midgard_reg_mode reg_mode, in print_vec_selectors_64() argument
436 midgard_reg_mode reg_mode, in print_vec_selectors() argument
440 assert(reg_mode != midgard_reg_mode_64); in print_vec_selectors()
[all …]
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
H A Ddisassemble.c129 midgard_reg_mode reg_mode) in validate_expand_mode() argument
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
137 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
142 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
404 midgard_reg_mode reg_mode, in print_vec_selectors_64() argument
436 midgard_reg_mode reg_mode, in print_vec_selectors() argument
440 assert(reg_mode != midgard_reg_mode_64); in print_vec_selectors()
[all …]
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
H A Ddisassemble.c129 midgard_reg_mode reg_mode) in validate_expand_mode() argument
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
137 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
142 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
404 midgard_reg_mode reg_mode, in print_vec_selectors_64() argument
436 midgard_reg_mode reg_mode, in print_vec_selectors() argument
440 assert(reg_mode != midgard_reg_mode_64); in print_vec_selectors()
[all …]
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
H A Ddisassemble.c129 midgard_reg_mode reg_mode) in validate_expand_mode() argument
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
137 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
142 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
404 midgard_reg_mode reg_mode, in print_vec_selectors_64() argument
436 midgard_reg_mode reg_mode, in print_vec_selectors() argument
440 assert(reg_mode != midgard_reg_mode_64); in print_vec_selectors()
[all …]
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
H A Ddisassemble.c129 midgard_reg_mode reg_mode) in validate_expand_mode() argument
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
137 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
142 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
404 midgard_reg_mode reg_mode, in print_vec_selectors_64() argument
439 midgard_reg_mode reg_mode, in print_vec_selectors() argument
443 assert(reg_mode != midgard_reg_mode_64); in print_vec_selectors()
[all …]
/dports/graphics/mesa-dri/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
/dports/lang/clover/mesa-21.3.6/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/panfrost/midgard/
H A Dmidgard_print.c112 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component() argument
141 reg_mode--; in mir_print_constant_component()
143 switch (reg_mode) { in mir_print_constant_component()
245 midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)); in mir_print_embedded_constant() local
266 swizzle[comp], reg_mode, in mir_print_embedded_constant()
/dports/lang/gnat_util/gcc-6-20180516/gcc/
H A Dauto-inc-dec.c605 machine_mode reg_mode = GET_MODE (inc_reg); in try_merge() local
660 return attempt_change (gen_rtx_PRE_INC (reg_mode, inc_reg), inc_reg); in try_merge()
672 return attempt_change (gen_rtx_PRE_DEC (reg_mode, inc_reg), inc_reg); in try_merge()
684 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
686 gen_rtx_PLUS (reg_mode, in try_merge()
695 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
697 gen_rtx_PLUS (reg_mode, in try_merge()
706 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
708 gen_rtx_PLUS (reg_mode, in try_merge()
717 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
[all …]
/dports/lang/gcc48/gcc-4.8.5/gcc/
H A Dauto-inc-dec.c615 enum machine_mode reg_mode = GET_MODE (inc_reg); in try_merge() local
670 return attempt_change (gen_rtx_PRE_INC (reg_mode, inc_reg), inc_reg); in try_merge()
682 return attempt_change (gen_rtx_PRE_DEC (reg_mode, inc_reg), inc_reg); in try_merge()
694 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
696 gen_rtx_PLUS (reg_mode, in try_merge()
705 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
707 gen_rtx_PLUS (reg_mode, in try_merge()
716 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
718 gen_rtx_PLUS (reg_mode, in try_merge()
727 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
[all …]
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/
H A Dauto-inc-dec.c615 enum machine_mode reg_mode = GET_MODE (inc_reg); in try_merge() local
670 return attempt_change (gen_rtx_PRE_INC (reg_mode, inc_reg), inc_reg); in try_merge()
682 return attempt_change (gen_rtx_PRE_DEC (reg_mode, inc_reg), inc_reg); in try_merge()
694 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
696 gen_rtx_PLUS (reg_mode, in try_merge()
705 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
707 gen_rtx_PLUS (reg_mode, in try_merge()
716 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
718 gen_rtx_PLUS (reg_mode, in try_merge()
727 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
[all …]
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/
H A Dauto-inc-dec.c615 enum machine_mode reg_mode = GET_MODE (inc_reg); in try_merge() local
670 return attempt_change (gen_rtx_PRE_INC (reg_mode, inc_reg), inc_reg); in try_merge()
682 return attempt_change (gen_rtx_PRE_DEC (reg_mode, inc_reg), inc_reg); in try_merge()
694 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
696 gen_rtx_PLUS (reg_mode, in try_merge()
705 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
707 gen_rtx_PLUS (reg_mode, in try_merge()
716 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
718 gen_rtx_PLUS (reg_mode, in try_merge()
727 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
[all …]
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/
H A Dauto-inc-dec.c605 machine_mode reg_mode = GET_MODE (inc_reg); in try_merge() local
660 return attempt_change (gen_rtx_PRE_INC (reg_mode, inc_reg), inc_reg); in try_merge()
672 return attempt_change (gen_rtx_PRE_DEC (reg_mode, inc_reg), inc_reg); in try_merge()
684 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
686 gen_rtx_PLUS (reg_mode, in try_merge()
695 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
697 gen_rtx_PLUS (reg_mode, in try_merge()
706 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, in try_merge()
708 gen_rtx_PLUS (reg_mode, in try_merge()
717 return attempt_change (gen_rtx_POST_MODIFY (reg_mode, in try_merge()
[all …]

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