1// 2// Copyright 2013 Ettus Research LLC 3// Copyright 2018 Ettus Research, a National Instruments Company 4// 5// SPDX-License-Identifier: LGPL-3.0-or-later 6// 7 8 9// radio top level module for b200 10// Contains all clock-rate DSP components, all radio and hardware controls and settings 11 12module radio_legacy 13 #( 14 parameter RADIO_FIFO_SIZE = 13, 15 parameter SAMPLE_FIFO_SIZE = 11, 16 parameter FP_GPIO = 0, 17 parameter NEW_HB_INTERP = 0, 18 parameter NEW_HB_DECIM = 0, 19 parameter SOURCE_FLOW_CONTROL = 0, 20 parameter USER_SETTINGS = 0, 21 parameter DEVICE = "SPARTAN6" 22 ) 23 (input radio_clk, input radio_rst, 24 input [31:0] rx, output reg [31:0] tx, 25 input [31:0] fe_gpio_in, output [31:0] fe_gpio_out, output [31:0] fe_gpio_ddr, 26 input [9:0] fp_gpio_in, output [9:0] fp_gpio_out, output [9:0] fp_gpio_ddr, 27 input pps, input time_sync, 28 input bus_clk, input bus_rst, 29 input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready, 30 output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready, 31 input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready, 32 output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready, 33 34 output reg [63:0] vita_time_b, 35 36 output [63:0] debug 37 ); 38 39 40 // /////////////////////////////////////////////////////////////////////////////// 41 // FIFO Interfacing to the bus clk domain 42 // in_tdata splits to tx_tdata and ctrl_tdata 43 // rx_tdata and resp_tdata get muxed to out_tdata 44 // Everything except rx flow control must cross in to radio_clk domain before further use 45 // _b signifies bus_clk domain, _r signifies radio_clk domain 46 47 wire [63:0] ctrl_tdata_r; 48 wire ctrl_tready_r, ctrl_tvalid_r; 49 wire ctrl_tlast_r; 50 51 wire [63:0] resp_tdata_r; 52 wire resp_tready_r, resp_tvalid_r; 53 wire resp_tlast_r; 54 55 wire [63:0] rx_tdata_r; 56 wire rx_tready_r, rx_tvalid_r; 57 wire rx_tlast_r; 58 59 wire [63:0] rx_err_tdata_r; 60 wire rx_err_tready_r, rx_err_tvalid_r; 61 wire rx_err_tlast_r; 62 63 wire [63:0] rx_prefc_tdata_r; 64 wire rx_prefc_tready_r, rx_prefc_tvalid_r; 65 wire rx_prefc_tlast_r; 66 67 wire [63:0] rx_postfc_tdata_r; 68 wire rx_postfc_tready_r, rx_postfc_tvalid_r; 69 wire rx_postfc_tlast_r; 70 71 wire [63:0] tx_tdata_r; 72 wire tx_tready_r, tx_tvalid_r; 73 wire tx_tlast_r; 74 75 wire [63:0] txresp_tdata, txresp_tdata_r; 76 wire txresp_tready, txresp_tready_r, txresp_tvalid, txresp_tvalid_r; 77 wire txresp_tlast, txresp_tlast_r; 78 79 wire [63:0] rmux_tdata_r; 80 wire rmux_tlast_r, rmux_tvalid_r, rmux_tready_r; 81 82 wire [31:0] tx_idle; 83 wire [3:0] ibs_state; 84 wire [63:0] rx_tdata_int; 85 wire rx_tready_int, rx_tvalid_int; 86 wire rx_tlast_int; 87 88 89 axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) ctrl_fifo 90 (.reset(bus_rst), 91 .i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}), 92 .o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r), .o_tdata({ctrl_tlast_r, ctrl_tdata_r})); 93 94 axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) tx_fifo 95 (.reset(bus_rst), 96 .i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}), 97 .o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r, tx_tdata_r})); 98 99 axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) resp_fifo 100 (.reset(radio_rst), 101 .i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}), 102 .o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata})); 103 104 axi_fifo_2clk #(.WIDTH(65), .SIZE(RADIO_FIFO_SIZE)) rx_fifo 105 (.reset(radio_rst), 106 .i_aclk(radio_clk), .i_tvalid(rx_tvalid_r), .i_tready(rx_tready_r), .i_tdata({rx_tlast_r, rx_tdata_r}), 107 .o_aclk(bus_clk), .o_tvalid(rx_tvalid_int), .o_tready(rx_tready_int), .o_tdata({rx_tlast_int, rx_tdata_int})); 108 109 axi_packet_gate #(.WIDTH(64), .SIZE(SAMPLE_FIFO_SIZE), .USE_AS_BUFF(0)) buffer_whole_pkt 110 ( 111 .clk(bus_clk), .reset(bus_rst), .clear(1'b0), 112 .i_tdata(rx_tdata_int), .i_tlast(rx_tlast_int), .i_terror(1'b0), .i_tvalid(rx_tvalid_int), .i_tready(rx_tready_int), 113 .o_tdata(rx_tdata), .o_tlast(rx_tlast), .o_tvalid(rx_tvalid), .o_tready(rx_tready)); 114 115 /////////////////////////////////////////////////////////////////////////////////////// 116 // Setting bus and controls 117 118 wire [63:0] ctrl_tdata_proc; 119 wire ctrl_tready_proc, ctrl_tvalid_proc; 120 wire ctrl_tlast_proc; 121 122 localparam SR_LOOPBACK = 8'd6; 123 localparam SR_SPI = 8'd8; 124 localparam SR_ATR = 8'd12; // thorugh 8'd18 125 localparam SR_TEST = 8'd21; 126 localparam SR_CODEC_IDLE = 8'd22; 127 localparam SR_READBACK = 8'd32; 128 localparam SR_TX_CTRL = 8'd64; 129 localparam SR_RX_CTRL = 8'd96; 130 localparam SR_TIME = 8'd128; 131 localparam SR_RX_FMT = 8'd136; 132 localparam SR_TX_FMT = 8'd138; 133 localparam SR_RX_DSP = 8'd144; 134 localparam SR_TX_DSP = 8'd184; 135 localparam SR_FP_GPIO = 8'd200; // thorugh 8'd206 136 localparam SR_USER_SR_BASE = 8'd253; 137 localparam SR_USER_RB_ADDR = 8'd255; 138 139 wire set_stb; 140 wire [7:0] set_addr; 141 wire [31:0] set_data; 142 wire [31:0] test_readback; 143 wire [9:0] fp_gpio_readback; 144 wire run_rx, run_tx; 145 wire rx_flow_ctrl_busy; 146 147 reg [63:0] rb_data; 148 wire [2:0] rb_addr; 149 150 wire [63:0] vita_time, vita_time_lastpps; 151 timekeeper_legacy #(.SR_TIME_HI(SR_TIME), .SR_TIME_LO(SR_TIME+1), .SR_TIME_CTRL(SR_TIME+2)) timekeeper 152 (.clk(radio_clk), .reset(radio_rst), .pps(pps), .sync_in(time_sync), .strobe(1'b1), 153 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 154 .vita_time(vita_time), .vita_time_lastpps(vita_time_lastpps), 155 .sync_out()); 156 157 wire [31:0] debug_radio_ctrl_proc; 158 radio_ctrl_proc radio_ctrl_proc 159 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 160 .ctrl_tdata(ctrl_tdata_proc), .ctrl_tlast(ctrl_tlast_proc), .ctrl_tvalid(ctrl_tvalid_proc), .ctrl_tready(ctrl_tready_proc), 161 .resp_tdata(resp_tdata_r), .resp_tlast(resp_tlast_r), .resp_tvalid(resp_tvalid_r), .resp_tready(resp_tready_r), 162 .vita_time(vita_time), 163 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 164 .ready(1'b1), .readback(rb_data), 165 .debug(debug_radio_ctrl_proc)); 166 167 reg [63:0] rb_data_user; 168generate 169 if (USER_SETTINGS == 1) begin 170 wire set_stb_user; 171 wire [7:0] set_addr_user; 172 wire [31:0] set_data_user; 173 wire [7:0] rb_addr_user; 174 175 user_settings #(.BASE(SR_USER_SR_BASE)) user_settings 176 (.clk(radio_clk), .rst(radio_rst), 177 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 178 .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user)); 179 180 setting_reg #(.my_addr(SR_USER_RB_ADDR), .awidth(8), .width(8)) user_rb_addr 181 (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), 182 .out(rb_addr_user), .changed()); 183 184 // ---------------------------------- 185 // Enter user settings registers here 186 // ---------------------------------- 187 188 // Example code for 32-bit settings registers and 64-bit readback registers 189 // 190 // To test this, modify the *_core.v file for your specific USRP and set 191 // USER_SETTINGS=1 for the parameters for the radio_legacy instantiation. 192 // 193 // You can then use the get_user_settings_iface() like this: 194 // 195 // auto usrp = multi_usrp::make("type=b200,enable_user_regs"); 196 // auto regs = usrp->get_user_settings_iface(0); 197 // regs->poke32(0, 0xCAFE); 198 // regs->poke32(4, 0xBEEF); 199 // std::cout << boost::format("0x%016X") % regs->peek64(0) << std::endl; 200 wire [31:0] user_reg_0_value, user_reg_1_value; 201 202 setting_reg #(.my_addr(8'd0), .awidth(8), .width(32)) user_reg_0 203 (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb_user), .addr(set_addr_user), .in(set_data_user), 204 .out(user_reg_0_value), .changed()); 205 206 setting_reg #(.my_addr(8'd1), .awidth(8), .width(32)) user_reg_1 207 (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb_user), .addr(set_addr_user), .in(set_data_user), 208 .out(user_reg_1_value), .changed()); 209 210 always @* begin 211 case(rb_addr_user) 212 8'd0 : rb_data_user <= {user_reg_1_value, user_reg_0_value}; 213 default : rb_data_user <= 64'd0; 214 endcase 215 end 216 217 end else begin //for USER_SETTINGS == 1 218 always @* rb_data_user <= 64'd0; 219 end 220endgenerate 221 222 always @* 223 case(rb_addr) 224 3'd0 : rb_data <= { 32'b0, test_readback }; 225 3'd1 : rb_data <= vita_time; 226 3'd2 : rb_data <= vita_time_lastpps; 227 3'd3 : rb_data <= {tx, rx}; 228 3'd4 : rb_data <= {54'h0,fp_gpio_readback}; 229 3'd5 : rb_data <= {59'h0,rx_flow_ctrl_busy,ibs_state[3:0]}; // Monitor state of RX state machine. 230// 3'd6 : rb_data <= <unused>; 231 3'd7 : rb_data <= rb_data_user; 232 default : rb_data <= 64'd0; 233 endcase // case (rb_addr) 234 235 // 236 // Sample VITA_TIME into the bus_clk domain for use by instrumentation. 237 // 238 wire [63:0] vita_time_b_int; 239 wire vita_time_b_valid; 240 241 axi_fifo_2clk #(.WIDTH(64), .SIZE(0)) vita_time_fifo 242 (.reset(radio_rst), 243 .i_aclk(radio_clk), .i_tvalid(1'b1), .i_tready(), .i_tdata(vita_time), 244 .o_aclk(bus_clk), .o_tvalid(vita_time_b_valid), .o_tready(1'b1), .o_tdata(vita_time_b_int)); 245 246 always @(posedge bus_clk) 247 if (vita_time_b_valid) 248 vita_time_b <= vita_time_b_int; 249 250 // Set this register to loop TX data directly to RX data. 251 setting_reg #(.my_addr(SR_LOOPBACK), .awidth(8), .width(1)) sr_loopback 252 (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), 253 .out(loopback), .changed()); 254 255 setting_reg #(.my_addr(SR_TEST), .awidth(8), .width(32)) sr_test 256 (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), 257 .out(test_readback), .changed()); 258 259 setting_reg #(.my_addr(SR_CODEC_IDLE), .awidth(8), .width(32)) sr_codec_idle 260 (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), 261 .out(tx_idle), .changed()); 262 263 setting_reg #(.my_addr(SR_READBACK), .awidth(8), .width(3)) sr_rdback 264 (.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data), 265 .out(rb_addr), .changed()); 266 267 //The fe_atr pins driven by this module are always configured as outputs so default 268 //the DDR (data direction register) to be all ones (outputs) so that the drive direction 269 //these lines does not change during/after resets. 270 gpio_atr #(.BASE(SR_ATR), .WIDTH(32), .FAB_CTRL_EN(0), .DEFAULT_DDR(32'hFFFFFFFF), .DEFAULT_IDLE(32'h00000000)) fe_gpio_atr 271 (.clk(radio_clk),.reset(radio_rst), 272 .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), 273 .rx(run_rx), .tx(run_tx), 274 .gpio_in(fe_gpio_in), .gpio_out(fe_gpio_out), .gpio_ddr(fe_gpio_ddr), 275 .gpio_out_fab(32'h00000000 /* no fabric control */), .gpio_sw_rb() ); 276 277 generate 278 if (FP_GPIO != 0) begin: add_fp_gpio 279 gpio_atr #(.BASE(SR_FP_GPIO), .WIDTH(10), .FAB_CTRL_EN(0)) fp_gpio_atr 280 (.clk(radio_clk),.reset(radio_rst), 281 .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), 282 .rx(run_rx), .tx(run_tx), 283 .gpio_in(fp_gpio_in), .gpio_out(fp_gpio_out), .gpio_ddr(fp_gpio_ddr), 284 .gpio_out_fab(10'h000 /* no fabric control */), .gpio_sw_rb(fp_gpio_readback)); 285 end 286 endgenerate 287 288 289 290 /////////////////////////////////////////////////////////////////////////////////////// 291 // Source flow control 292 293generate 294 if (SOURCE_FLOW_CONTROL == 1) begin 295 296 localparam SID_PREFIX_CTRL = 2'd0; 297 localparam SID_PREFIX_FC = 2'd1; 298 299 wire [63:0] ctrl_tdata_fc; 300 wire ctrl_tready_fc, ctrl_tvalid_fc; 301 wire ctrl_tlast_fc; 302 303 wire [63:0] ctrl_hdr; 304 wire [1:0] ctrl_dest; 305 306 assign ctrl_dest = (ctrl_hdr[1:0] == SID_PREFIX_FC) ? 2'd1 : 2'd0; 307 308 axi_demux4 #(.ACTIVE_CHAN(4'b0011), .WIDTH(64), .BUFFER(1)) demux_proc_fc 309 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 310 .header(ctrl_hdr), .dest(ctrl_dest), 311 .i_tdata(ctrl_tdata_r), .i_tlast(ctrl_tlast_r), .i_tvalid(ctrl_tvalid_r), .i_tready(ctrl_tready_r), //Input 312 .o0_tdata(ctrl_tdata_proc), .o0_tlast(ctrl_tlast_proc), .o0_tvalid(ctrl_tvalid_proc), .o0_tready(ctrl_tready_proc), //Settings/Readback 313 .o1_tdata(ctrl_tdata_fc), .o1_tlast(ctrl_tlast_fc), .o1_tvalid(ctrl_tvalid_fc), .o1_tready(ctrl_tready_fc), //Flow control 314 .o2_tdata(), .o2_tlast(), .o2_tvalid(), .o2_tready(1'b0), //Unused 315 .o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b0)); //Unused 316 317 source_flow_control_legacy #(.BASE(SR_RX_CTRL+6)) rx_sfc 318 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 319 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 320 .fc_tdata(ctrl_tdata_fc), .fc_tlast(ctrl_tlast_fc), .fc_tvalid(ctrl_tvalid_fc), .fc_tready(ctrl_tready_fc), //Flow control In 321 .in_tdata(rx_prefc_tdata_r), .in_tlast(rx_prefc_tlast_r), .in_tvalid(rx_prefc_tvalid_r), .in_tready(rx_prefc_tready_r), //RX Input 322 .out_tdata(rx_postfc_tdata_r), .out_tlast(rx_postfc_tlast_r), .out_tvalid(rx_postfc_tvalid_r), .out_tready(rx_postfc_tready_r), //RX Output 323 .busy(rx_flow_ctrl_busy)); 324 325 end else begin //for SOURCE_FLOW_CONTROL == 1 326 327 assign ctrl_tdata_proc = ctrl_tdata_r; 328 assign ctrl_tlast_proc = ctrl_tlast_r; 329 assign ctrl_tvalid_proc = ctrl_tvalid_r; 330 assign ctrl_tready_r = ctrl_tready_proc; 331 332 assign rx_postfc_tdata_r = rx_prefc_tdata_r; 333 assign rx_postfc_tlast_r = rx_prefc_tlast_r; 334 assign rx_postfc_tvalid_r = rx_prefc_tvalid_r; 335 assign rx_prefc_tready_r = rx_postfc_tready_r; 336 337 assign rx_flow_ctrl_busy = 1'b0; 338 339 end 340 341endgenerate 342 343 // ///////////////////////////////////////////////////////////////////////////////// 344 // TX Chain 345 346 wire [175:0] txsample_tdata; 347 wire txsample_tvalid, txsample_tready; 348 wire [31:0] sample_tx; 349 wire ack_or_error, packet_consumed; 350 wire [11:0] seqnum; 351 wire [63:0] error_code; 352 wire [31:0] sid; 353 wire [23:0] tx_fe_i, tx_fe_q; 354 355 wire [31:0] debug_tx_control; 356 357 always @(posedge radio_clk) begin 358 tx[31:16] <= (run_tx) ? tx_fe_i[23:8] : tx_idle[31:16]; 359 tx[15:0] <= (run_tx) ? tx_fe_q[23:8] : tx_idle[15:0]; 360 end 361 362 wire [63:0] tx_tdata_i; wire tx_tlast_i, tx_tvalid_i, tx_tready_i; 363 364 new_tx_deframer tx_deframer 365 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 366 .i_tdata(tx_tdata_i), .i_tlast(tx_tlast_i), .i_tvalid(tx_tvalid_i), .i_tready(tx_tready_i), 367 .sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready), 368 .debug()); 369 370 new_tx_control #(.BASE(SR_TX_CTRL)) tx_control 371 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 372 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 373 .vita_time(vita_time), 374 .ack_or_error(ack_or_error), .packet_consumed(packet_consumed), 375 .seqnum(seqnum), .error_code(error_code), .sid(sid), 376 .sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready), 377 .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), 378 .debug(debug_tx_control)); 379 380 tx_responder #(.BASE(SR_TX_CTRL+2)) tx_responder 381 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 382 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 383 .ack_or_error(ack_or_error), .packet_consumed(packet_consumed), 384 .seqnum(seqnum), .error_code(error_code), .sid(sid), 385 .vita_time(vita_time), 386 .o_tdata(txresp_tdata_r), .o_tlast(txresp_tlast_r), .o_tvalid(txresp_tvalid_r), .o_tready(txresp_tready_r)); 387 388 wire [31:0] debug_duc_chain; 389 duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0), .WIDTH(24), .NEW_HB_INTERP(NEW_HB_INTERP),.DEVICE(DEVICE)) duc_chain 390 (.clk(radio_clk), .rst(radio_rst), .clr(1'b0), 391 .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), 392 .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q), 393 .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), 394 .debug(debug_duc_chain) ); 395 396`ifdef DELETE_FORMAT_CONVERSION 397 assign tx_tdata_i = tx_tdata_r; 398 assign tx_tlast_i = tx_tlast_r; 399 assign tx_tvalid_i = tx_tvalid_r; 400 assign tx_tready_r = tx_tready_i; 401`else 402 chdr_xxxx_to_16sc_chain #(.BASE(SR_TX_FMT)) convert_xxxx_to_16sc 403 (.clk(radio_clk), .reset(radio_rst), 404 .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), 405 .i_tdata(tx_tdata_r), .i_tlast(tx_tlast_r), .i_tvalid(tx_tvalid_r), .i_tready(tx_tready_r), 406 .o_tdata(tx_tdata_i), .o_tlast(tx_tlast_i), .o_tvalid(tx_tvalid_i), .o_tready(tx_tready_i), 407 .debug()); 408`endif // !`ifdef DELETE_FORMAT_CONVERSION 409 410 // ///////////////////////////////////////////////////////////////////////////////// 411 // RX Chain 412 413 wire full, eob_rx; 414 wire strobe_rx; 415 wire [31:0] sample_rx; 416 wire [31:0] rx_sid; 417 wire [11:0] rx_seqnum; 418 wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i; 419 420 wire [31:0] debug_rx_framer; 421 new_rx_framer #(.BASE(SR_RX_CTRL+4),.SAMPLE_FIFO_SIZE(SAMPLE_FIFO_SIZE)) new_rx_framer 422 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 423 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 424 .vita_time(vita_time), 425 .strobe(strobe_rx), .sample(sample_rx), .run(run_rx), .eob(eob_rx), .full(full), 426 .sid(rx_sid), .seqnum(rx_seqnum), 427 .o_tdata(rx_tdata_i), .o_tlast(rx_tlast_i), .o_tvalid(rx_tvalid_i), .o_tready(rx_tready_i), 428 .debug(debug_rx_framer)); 429 430 wire [31:0] debug_rx_control; 431 new_rx_control #(.BASE(SR_RX_CTRL)) new_rx_control 432 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 433 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), 434 .vita_time(vita_time), 435 .strobe(strobe_rx), .run(run_rx), .eob(eob_rx), .full(full), 436 .sid(rx_sid), .seqnum(rx_seqnum), 437 .err_tdata(rx_err_tdata_r), .err_tlast(rx_err_tlast_r), .err_tvalid(rx_err_tvalid_r), .err_tready(rx_err_tready_r), 438 .ibs_state(ibs_state), 439 .debug(debug_rx_control)); 440 441 wire [31:0] debug_ddc_chain; 442 443 // Digital Loopback TX -> RX (Pipeline immediately inside rx_frontend). 444 wire [31:0] rx_fe = loopback ? tx : rx; 445 446 ddc_chain #(.BASE(SR_RX_DSP), .DSPNO(0), .WIDTH(24), .NEW_HB_DECIM(NEW_HB_DECIM), .DEVICE(DEVICE)) ddc_chain 447 (.clk(radio_clk), .rst(radio_rst), .clr(1'b0), 448 .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), 449 .rx_fe_i({rx_fe[31:16],8'd0}),.rx_fe_q({rx_fe[15:0],8'd0}), 450 .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), 451 .debug(debug_ddc_chain) ); 452 453`ifdef DELETE_FORMAT_CONVERSION 454 assign rx_prefc_tdata_r = rx_tdata_i; 455 assign rx_prefc_tlast_r = rx_tlast_i; 456 assign rx_prefc_tvalid_r = rx_tvalid_i; 457 assign rx_tready_i = rx_prefc_tready_r; 458`else 459 chdr_16sc_to_xxxx_chain #(.BASE(SR_RX_FMT)) convert_16sc_to_xxxx 460 (.clk(radio_clk), .reset(radio_rst), 461 .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), 462 .i_tdata(rx_tdata_i), .i_tlast(rx_tlast_i), .i_tvalid(rx_tvalid_i), .i_tready(rx_tready_i), 463 .o_tdata(rx_prefc_tdata_r), .o_tlast(rx_prefc_tlast_r), .o_tvalid(rx_prefc_tvalid_r), .o_tready(rx_prefc_tready_r), 464 .debug()); 465`endif 466 // ///////////////////////////////////////////////////////////////////////////////// 467 // RX Channel Muxing 468 469 axi_mux4 #(.PRIO(1), .WIDTH(64), .BUFFER(1)) rx_mux 470 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 471 .i0_tdata(rx_postfc_tdata_r), .i0_tlast(rx_postfc_tlast_r), .i0_tvalid(rx_postfc_tvalid_r), .i0_tready(rx_postfc_tready_r), 472 .i1_tdata(rx_err_tdata_r), .i1_tlast(rx_err_tlast_r), .i1_tvalid(rx_err_tvalid_r), .i1_tready(rx_err_tready_r), 473 .i2_tdata(64'h0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(), 474 .i3_tdata(64'h0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(), 475 .o_tdata(rx_tdata_r), .o_tlast(rx_tlast_r), .o_tvalid(rx_tvalid_r), .o_tready(rx_tready_r)); 476 477 // ///////////////////////////////////////////////////////////////////////////////// 478 // Response Channel Muxing 479 480 axi_mux4 #(.PRIO(0), .WIDTH(64)) response_mux 481 (.clk(radio_clk), .reset(radio_rst), .clear(1'b0), 482 .i0_tdata(txresp_tdata_r), .i0_tlast(txresp_tlast_r), .i0_tvalid(txresp_tvalid_r), .i0_tready(txresp_tready_r), 483 .i1_tdata(resp_tdata_r), .i1_tlast(resp_tlast_r), .i1_tvalid(resp_tvalid_r), .i1_tready(resp_tready_r), 484 .i2_tdata(64'h0), .i2_tlast(1'b0), .i2_tvalid(1'b0), .i2_tready(), 485 .i3_tdata(64'h0), .i3_tlast(1'b0), .i3_tvalid(1'b0), .i3_tready(), 486 .o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r)); 487 488 489 490 491 /******************************************************************* 492 * Debug only logic below here. 493 ******************************************************************/ 494 assign debug = 0; 495 496endmodule // radio_legacy 497