riscv_masked_atomicrmw_nand_i32 (reference) in projects: dports

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Searched refs:riscv_masked_atomicrmw_nand_i32 (Results 1 – 17 of 17) sorted by relevance

/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
H A D	IntrinsicsRISCV.h	`22 riscv_masked_atomicrmw_nand_i32, // llvm.riscv.masked.atomicrmw.nand.i32 enumerator`
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`189 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 1742 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp32()`
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`223 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 2545 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`249 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 2774 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`281 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 2885 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`257 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 2808 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`257 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 2808 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`280 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 2865 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`312 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 3328 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`503 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 4356 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`503 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 4356 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`898 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 8766 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`898 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 8766 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`898 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 8766 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`898 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 8766 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`898 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 8766 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	`963 case Intrinsic::riscv_masked_atomicrmw_nand_i32: in getTgtMemIntrinsic() 9566 return Intrinsic::riscv_masked_atomicrmw_nand_i32; in getIntrinsicForMaskedAtomicRMWBinOp()`