Searched refs:rxdfifo_rdata (Results 1 – 3 of 3) sorted by relevance
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/ |
| H A D | rx_dequeue.v | 46 clk_156m25, reset_156m25_n, rxdfifo_rdata, rxdfifo_rstatus,
53 input [63:0] rxdfifo_rdata; port
135 pkt_rx_data <= {rxdfifo_rdata[7:0],
136 rxdfifo_rdata[15:8],
137 rxdfifo_rdata[23:16],
138 rxdfifo_rdata[31:24],
139 rxdfifo_rdata[39:32],
140 rxdfifo_rdata[47:40],
141 rxdfifo_rdata[55:48],
142 rxdfifo_rdata[63:56]};
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| H A D | rx_data_fifo.v | 43 rxdfifo_wfull, rxdfifo_rdata, rxdfifo_rstatus, rxdfifo_rempty,
63 output [63:0] rxdfifo_rdata; port
88 .rdata ({rxdfifo_rstatus, rxdfifo_rdata}),
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| H A D | xge_mac.v | 104 wire [63:0] rxdfifo_rdata; // From rx_data_fifo0 of rx_data_fifo.v net
184 .rxdfifo_rdata (rxdfifo_rdata[63:0]),
193 .rxdfifo_rdata (rxdfifo_rdata[63:0]),
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