1////////////////////////////////////////////////////////////////////// 2//// //// 3//// File name "rx_data_fifo.v" //// 4//// //// 5//// This file is part of the "10GE MAC" project //// 6//// http://www.opencores.org/cores/xge_mac/ //// 7//// //// 8//// Author(s): //// 9//// - A. Tanguay (antanguay@opencores.org) //// 10//// //// 11////////////////////////////////////////////////////////////////////// 12//// //// 13//// Copyright (C) 2008 AUTHORS. All rights reserved. //// 14//// //// 15//// This source file may be used and distributed without //// 16//// restriction provided that this copyright statement is not //// 17//// removed from the file and that any derivative work contains //// 18//// the original copyright notice and the associated disclaimer. //// 19//// //// 20//// This source file is free software; you can redistribute it //// 21//// and/or modify it under the terms of the GNU Lesser General //// 22//// Public License as published by the Free Software Foundation; //// 23//// either version 2.1 of the License, or (at your option) any //// 24//// later version. //// 25//// //// 26//// This source is distributed in the hope that it will be //// 27//// useful, but WITHOUT ANY WARRANTY; without even the implied //// 28//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// 29//// PURPOSE. See the GNU Lesser General Public License for more //// 30//// details. //// 31//// //// 32//// You should have received a copy of the GNU Lesser General //// 33//// Public License along with this source; if not, download it //// 34//// from http://www.opencores.org/lgpl.shtml //// 35//// //// 36////////////////////////////////////////////////////////////////////// 37 38 39`include "defines.v" 40 41module rx_data_fifo(/*AUTOARG*/ 42 // Outputs 43 rxdfifo_wfull, rxdfifo_rdata, rxdfifo_rstatus, rxdfifo_rempty, 44 rxdfifo_ralmost_empty, 45 // Inputs 46 clk_xgmii_rx, clk_156m25, reset_xgmii_rx_n, reset_156m25_n, 47 rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxdfifo_ren 48 ); 49 50input clk_xgmii_rx; 51input clk_156m25; 52input reset_xgmii_rx_n; 53input reset_156m25_n; 54 55input [63:0] rxdfifo_wdata; 56input [7:0] rxdfifo_wstatus; 57input rxdfifo_wen; 58 59input rxdfifo_ren; 60 61output rxdfifo_wfull; 62 63output [63:0] rxdfifo_rdata; 64output [7:0] rxdfifo_rstatus; 65output rxdfifo_rempty; 66output rxdfifo_ralmost_empty; 67 68generic_fifo #( 69 .DWIDTH (72), 70 .AWIDTH (`RX_DATA_FIFO_AWIDTH), 71 .REGISTER_READ (0), 72 .EARLY_READ (1), 73 .CLOCK_CROSSING (1), 74 .ALMOST_EMPTY_THRESH (4), 75 .MEM_TYPE (`MEM_AUTO_XILINX) 76) 77fifo0( 78 .wclk (clk_xgmii_rx), 79 .wrst_n (reset_xgmii_rx_n), 80 .wen (rxdfifo_wen), 81 .wdata ({rxdfifo_wstatus, rxdfifo_wdata}), 82 .wfull (rxdfifo_wfull), 83 .walmost_full (), 84 85 .rclk (clk_156m25), 86 .rrst_n (reset_156m25_n), 87 .ren (rxdfifo_ren), 88 .rdata ({rxdfifo_rstatus, rxdfifo_rdata}), 89 .rempty (rxdfifo_rempty), 90 .ralmost_empty (rxdfifo_ralmost_empty) 91); 92 93 94endmodule 95 96