Searched refs:rxdfifo_wfull (Results 1 – 3 of 3) sorted by relevance
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/ |
H A D | rx_data_fifo.v | 43 rxdfifo_wfull, rxdfifo_rdata, rxdfifo_rstatus, rxdfifo_rempty, 61 output rxdfifo_wfull; port 82 .wfull (rxdfifo_wfull),
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H A D | xge_mac.v | 110 wire rxdfifo_wfull; // From rx_data_fifo0 of rx_data_fifo.v net 164 .rxdfifo_wfull (rxdfifo_wfull), 192 .rxdfifo_wfull (rxdfifo_wfull),
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H A D | rx_enqueue.v | 49 clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, rxdfifo_wfull, 64 input rxdfifo_wfull; port 708 or rxdfifo_wfull or rxhfifo_ralmost_empty_d1 or rxhfifo_rdata 734 if (rxhfifo_ren_d1 && rxdfifo_wfull && !next_drop_data) begin
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