| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/crossbar/ |
| H A D | chdr_xb_ingress_buff.v | 36 input wire s_axis_chdr_tvalid, port
170 end else if (s_axis_chdr_tvalid & s_axis_chdr_tready) begin
198 assign s_axis_chdr_tready = s_axis_chdr_tvalid &&
205 wire chdr_header_stb = s_axis_chdr_tvalid &&
232 assign gate_i_tvalid = s_axis_chdr_tready && s_axis_chdr_tvalid;
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/utils/rfnoc_blocktool/templates/modules/ |
| H A D | axis_chdr_modules_template.mako | 21 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}+i]),
41 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}]),
82 .s_axis_chdr_tvalid (s_${port_name}_chdr_tvalid[i]),
102 .s_axis_chdr_tvalid (s_${port_name}_chdr_tvalid),
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| H A D | axis_data_modules_template.mako | 31 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}+i]),
64 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}]),
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| H A D | axis_pyld_ctxt_modules_template.mako | 32 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}+i]),
66 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}]),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/core/ |
| H A D | chdr_to_chdr_data.v | 29 input wire s_axis_chdr_tvalid, port
50 .s_axis_tvalid(s_axis_chdr_tvalid), .s_axis_tready(s_axis_chdr_tready),
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| H A D | chdr_stream_endpoint.v | 63 input wire s_axis_chdr_tvalid, port
158 .i_tvalid(s_axis_chdr_tvalid),
199 .s_axis_chdr_tvalid(mgmt_i_tvalid), .s_axis_chdr_tready(mgmt_i_tready),
498 .s_axis_chdr_tvalid(data_i_tvalid),
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| H A D | chdr_mgmt_pkt_handler.v | 44 input wire s_axis_chdr_tvalid, port
111 .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
138 assign s_mgmt_tvalid = s_axis_chdr_tvalid;
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| H A D | chdr_stream_input.v | 44 input wire s_axis_chdr_tvalid, port
84 .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
93 .i_tlast(s_axis_chdr_tlast), .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
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| H A D | chdr_to_axis_pyld_ctxt.v | 57 input wire s_axis_chdr_tvalid, port
97 .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
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| H A D | chdr_to_axis_data.v | 49 input wire s_axis_chdr_tvalid, port
89 .i_tvalid(s_axis_chdr_tvalid), .i_tready(s_axis_chdr_tready),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_split_stream/ |
| H A D | noc_shell_split_stream.v | 154 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]),
183 .s_axis_chdr_tvalid (s_out_chdr_tvalid[i]),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/ |
| H A D | noc_shell_switchboard.v | 206 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[i]),
235 .s_axis_chdr_tvalid (s_out_chdr_tvalid[i]),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/ |
| H A D | noc_shell_axi_ram_fifo.v | 228 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0+i]),
257 .s_axis_chdr_tvalid (s_out_chdr_tvalid[i]),
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| H A D | rfnoc_block_axi_ram_fifo.v | 229 wire [ NUM_PORTS-1:0] s_axis_chdr_tvalid; net
278 .s_out_chdr_tvalid (s_axis_chdr_tvalid),
401 .m_axis_tvalid (s_axis_chdr_tvalid[i]),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/ |
| H A D | noc_shell_addsub.v | 217 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0]),
250 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[1]),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ |
| H A D | n310_rfnoc_image_core.v | 280 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
341 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
402 .s_axis_chdr_tvalid (xb_to_ep2_tvalid ),
463 .s_axis_chdr_tvalid (xb_to_ep3_tvalid ),
524 .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
585 .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
646 .s_axis_chdr_tvalid (xb_to_ep6_tvalid ),
707 .s_axis_chdr_tvalid (xb_to_ep7_tvalid ),
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| H A D | n310_bist_image_core.v | 264 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
325 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
386 .s_axis_chdr_tvalid (xb_to_ep2_tvalid ),
447 .s_axis_chdr_tvalid (xb_to_ep3_tvalid ),
508 .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
569 .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
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| H A D | n300_bist_image_core.v | 230 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
291 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
352 .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
413 .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
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| H A D | n300_rfnoc_image_core.v | 230 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
291 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
352 .s_axis_chdr_tvalid (xb_to_ep2_tvalid ),
413 .s_axis_chdr_tvalid (xb_to_ep3_tvalid ),
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| H A D | n320_bist_image_core.v | 248 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
309 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
370 .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
431 .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/ |
| H A D | noc_shell_null_src_sink.v | 251 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[0]),
284 .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[1]),
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ |
| H A D | x310_rfnoc_image_core.v | 265 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
326 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
387 .s_axis_chdr_tvalid (xb_to_ep2_tvalid ),
448 .s_axis_chdr_tvalid (xb_to_ep3_tvalid ),
509 .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
570 .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
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| H A D | x300_rfnoc_image_core.v | 265 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
326 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
387 .s_axis_chdr_tvalid (xb_to_ep2_tvalid ),
448 .s_axis_chdr_tvalid (xb_to_ep3_tvalid ),
509 .s_axis_chdr_tvalid (xb_to_ep4_tvalid ),
570 .s_axis_chdr_tvalid (xb_to_ep5_tvalid ),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
| H A D | e320_rfnoc_image_core.v | 221 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
282 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
343 .s_axis_chdr_tvalid (xb_to_ep2_tvalid ),
404 .s_axis_chdr_tvalid (xb_to_ep3_tvalid ),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/ |
| H A D | e310_rfnoc_image_core.v | 149 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ),
210 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ),
|