1// 2// Copyright 2019 Ettus Research, A National Instruments Brand 3// 4// SPDX-License-Identifier: LGPL-3.0-or-later 5// 6 7// Module: rfnoc_image_core (for n310) 8// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) 9// Re-running that tool will overwrite this file! 10// File generated on: 2019-11-08T15:58:14.371732 11// Source: ./n3xx/n310_bist_image_core.yml 12// Source SHA256: 1a9ffb97d9678e700ad2aa172d206b6be9af30c7c0b014c21007d1de028a59d4 13 14module rfnoc_image_core #( 15 parameter [15:0] PROTOVER = {8'd1, 8'd0} 16)( 17 // Clocks 18 input wire chdr_aclk, 19 input wire ctrl_aclk, 20 input wire core_arst, 21 input wire radio_clk, 22 input wire dram_clk, 23 // Basic 24 input wire [15:0] device_id, 25//// IO ports ////////////////////////////////// 26// ctrlport_radio0 27 output wire [ 1-1:0] m_ctrlport_radio0_req_wr, 28 output wire [ 1-1:0] m_ctrlport_radio0_req_rd, 29 output wire [ 20-1:0] m_ctrlport_radio0_req_addr, 30 output wire [ 32-1:0] m_ctrlport_radio0_req_data, 31 output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, 32 output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, 33 output wire [ 64-1:0] m_ctrlport_radio0_req_time, 34 input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, 35 input wire [ 2-1:0] m_ctrlport_radio0_resp_status, 36 input wire [ 32-1:0] m_ctrlport_radio0_resp_data, 37// ctrlport_radio1 38 output wire [ 1-1:0] m_ctrlport_radio1_req_wr, 39 output wire [ 1-1:0] m_ctrlport_radio1_req_rd, 40 output wire [ 20-1:0] m_ctrlport_radio1_req_addr, 41 output wire [ 32-1:0] m_ctrlport_radio1_req_data, 42 output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, 43 output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, 44 output wire [ 64-1:0] m_ctrlport_radio1_req_time, 45 input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, 46 input wire [ 2-1:0] m_ctrlport_radio1_resp_status, 47 input wire [ 32-1:0] m_ctrlport_radio1_resp_data, 48// time_keeper 49 input wire [ 64-1:0] radio_time, 50// x300_radio0 51 input wire [ 64-1:0] radio_rx_data_radio0, 52 input wire [ 2-1:0] radio_rx_stb_radio0, 53 output wire [ 2-1:0] radio_rx_running_radio0, 54 output wire [ 64-1:0] radio_tx_data_radio0, 55 input wire [ 2-1:0] radio_tx_stb_radio0, 56 output wire [ 2-1:0] radio_tx_running_radio0, 57// x300_radio1 58 input wire [ 64-1:0] radio_rx_data_radio1, 59 input wire [ 2-1:0] radio_rx_stb_radio1, 60 output wire [ 2-1:0] radio_rx_running_radio1, 61 output wire [ 64-1:0] radio_tx_data_radio1, 62 input wire [ 2-1:0] radio_tx_stb_radio1, 63 output wire [ 2-1:0] radio_tx_running_radio1, 64// dram 65 input wire [ 1-1:0] axi_rst, 66 output wire [ 4-1:0] m_axi_awid, 67 output wire [128-1:0] m_axi_awaddr, 68 output wire [ 32-1:0] m_axi_awlen, 69 output wire [ 12-1:0] m_axi_awsize, 70 output wire [ 8-1:0] m_axi_awburst, 71 output wire [ 4-1:0] m_axi_awlock, 72 output wire [ 16-1:0] m_axi_awcache, 73 output wire [ 12-1:0] m_axi_awprot, 74 output wire [ 16-1:0] m_axi_awqos, 75 output wire [ 16-1:0] m_axi_awregion, 76 output wire [ 4-1:0] m_axi_awuser, 77 output wire [ 4-1:0] m_axi_awvalid, 78 input wire [ 4-1:0] m_axi_awready, 79 output wire [256-1:0] m_axi_wdata, 80 output wire [ 32-1:0] m_axi_wstrb, 81 output wire [ 4-1:0] m_axi_wlast, 82 output wire [ 4-1:0] m_axi_wuser, 83 output wire [ 4-1:0] m_axi_wvalid, 84 input wire [ 4-1:0] m_axi_wready, 85 input wire [ 4-1:0] m_axi_bid, 86 input wire [ 8-1:0] m_axi_bresp, 87 input wire [ 4-1:0] m_axi_buser, 88 input wire [ 4-1:0] m_axi_bvalid, 89 output wire [ 4-1:0] m_axi_bready, 90 output wire [ 4-1:0] m_axi_arid, 91 output wire [128-1:0] m_axi_araddr, 92 output wire [ 32-1:0] m_axi_arlen, 93 output wire [ 12-1:0] m_axi_arsize, 94 output wire [ 8-1:0] m_axi_arburst, 95 output wire [ 4-1:0] m_axi_arlock, 96 output wire [ 16-1:0] m_axi_arcache, 97 output wire [ 12-1:0] m_axi_arprot, 98 output wire [ 16-1:0] m_axi_arqos, 99 output wire [ 16-1:0] m_axi_arregion, 100 output wire [ 4-1:0] m_axi_aruser, 101 output wire [ 4-1:0] m_axi_arvalid, 102 input wire [ 4-1:0] m_axi_arready, 103 input wire [ 4-1:0] m_axi_rid, 104 input wire [256-1:0] m_axi_rdata, 105 input wire [ 8-1:0] m_axi_rresp, 106 input wire [ 4-1:0] m_axi_rlast, 107 input wire [ 4-1:0] m_axi_ruser, 108 input wire [ 4-1:0] m_axi_rvalid, 109 output wire [ 4-1:0] m_axi_rready, 110 // Transport 0 (eth0 1G) 111 input wire [64-1:0] s_eth0_tdata, 112 input wire s_eth0_tlast, 113 input wire s_eth0_tvalid, 114 output wire s_eth0_tready, 115 output wire [64-1:0] m_eth0_tdata, 116 output wire m_eth0_tlast, 117 output wire m_eth0_tvalid, 118 input wire m_eth0_tready, 119 // Transport 1 (eth1 10G) 120 input wire [64-1:0] s_eth1_tdata, 121 input wire s_eth1_tlast, 122 input wire s_eth1_tvalid, 123 output wire s_eth1_tready, 124 output wire [64-1:0] m_eth1_tdata, 125 output wire m_eth1_tlast, 126 output wire m_eth1_tvalid, 127 input wire m_eth1_tready, 128 // Transport 2 (dma dma) 129 input wire [64-1:0] s_dma_tdata, 130 input wire s_dma_tlast, 131 input wire s_dma_tvalid, 132 output wire s_dma_tready, 133 output wire [64-1:0] m_dma_tdata, 134 output wire m_dma_tlast, 135 output wire m_dma_tvalid, 136 input wire m_dma_tready 137); 138 139 localparam CHDR_W = 64; 140 localparam MTU = 10; 141 localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; 142 143 wire rfnoc_chdr_clk, rfnoc_chdr_rst; 144 wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; 145 146 // ---------------------------------------------------- 147 // CHDR Crossbar 148 // ---------------------------------------------------- 149 wire [CHDR_W-1:0] xb_to_ep0_tdata ; 150 wire xb_to_ep0_tlast ; 151 wire xb_to_ep0_tvalid; 152 wire xb_to_ep0_tready; 153 wire [CHDR_W-1:0] ep0_to_xb_tdata ; 154 wire ep0_to_xb_tlast ; 155 wire ep0_to_xb_tvalid; 156 wire ep0_to_xb_tready; 157 wire [CHDR_W-1:0] xb_to_ep1_tdata ; 158 wire xb_to_ep1_tlast ; 159 wire xb_to_ep1_tvalid; 160 wire xb_to_ep1_tready; 161 wire [CHDR_W-1:0] ep1_to_xb_tdata ; 162 wire ep1_to_xb_tlast ; 163 wire ep1_to_xb_tvalid; 164 wire ep1_to_xb_tready; 165 wire [CHDR_W-1:0] xb_to_ep2_tdata ; 166 wire xb_to_ep2_tlast ; 167 wire xb_to_ep2_tvalid; 168 wire xb_to_ep2_tready; 169 wire [CHDR_W-1:0] ep2_to_xb_tdata ; 170 wire ep2_to_xb_tlast ; 171 wire ep2_to_xb_tvalid; 172 wire ep2_to_xb_tready; 173 wire [CHDR_W-1:0] xb_to_ep3_tdata ; 174 wire xb_to_ep3_tlast ; 175 wire xb_to_ep3_tvalid; 176 wire xb_to_ep3_tready; 177 wire [CHDR_W-1:0] ep3_to_xb_tdata ; 178 wire ep3_to_xb_tlast ; 179 wire ep3_to_xb_tvalid; 180 wire ep3_to_xb_tready; 181 wire [CHDR_W-1:0] xb_to_ep4_tdata ; 182 wire xb_to_ep4_tlast ; 183 wire xb_to_ep4_tvalid; 184 wire xb_to_ep4_tready; 185 wire [CHDR_W-1:0] ep4_to_xb_tdata ; 186 wire ep4_to_xb_tlast ; 187 wire ep4_to_xb_tvalid; 188 wire ep4_to_xb_tready; 189 wire [CHDR_W-1:0] xb_to_ep5_tdata ; 190 wire xb_to_ep5_tlast ; 191 wire xb_to_ep5_tvalid; 192 wire xb_to_ep5_tready; 193 wire [CHDR_W-1:0] ep5_to_xb_tdata ; 194 wire ep5_to_xb_tlast ; 195 wire ep5_to_xb_tvalid; 196 wire ep5_to_xb_tready; 197 198 chdr_crossbar_nxn #( 199 .CHDR_W (CHDR_W), 200 .NPORTS (9), 201 .DEFAULT_PORT (0), 202 .MTU (MTU), 203 .ROUTE_TBL_SIZE (6), 204 .MUX_ALLOC ("ROUND-ROBIN"), 205 .OPTIMIZE ("AREA"), 206 .NPORTS_MGMT (3), 207 .EXT_RTCFG_PORT (0), 208 .PROTOVER (PROTOVER) 209 ) chdr_xb_i ( 210 .clk (rfnoc_chdr_clk), 211 .reset (rfnoc_chdr_rst), 212 .device_id (device_id), 213 .s_axis_tdata ({ep5_to_xb_tdata, ep4_to_xb_tdata, ep3_to_xb_tdata, ep2_to_xb_tdata, ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata, s_eth1_tdata, s_eth0_tdata}), 214 .s_axis_tlast ({ep5_to_xb_tlast, ep4_to_xb_tlast, ep3_to_xb_tlast, ep2_to_xb_tlast, ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast, s_eth1_tlast, s_eth0_tlast}), 215 .s_axis_tvalid ({ep5_to_xb_tvalid, ep4_to_xb_tvalid, ep3_to_xb_tvalid, ep2_to_xb_tvalid, ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid, s_eth1_tvalid, s_eth0_tvalid}), 216 .s_axis_tready ({ep5_to_xb_tready, ep4_to_xb_tready, ep3_to_xb_tready, ep2_to_xb_tready, ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready, s_eth1_tready, s_eth0_tready}), 217 .m_axis_tdata ({xb_to_ep5_tdata, xb_to_ep4_tdata, xb_to_ep3_tdata, xb_to_ep2_tdata, xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata, m_eth1_tdata, m_eth0_tdata}), 218 .m_axis_tlast ({xb_to_ep5_tlast, xb_to_ep4_tlast, xb_to_ep3_tlast, xb_to_ep2_tlast, xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast, m_eth1_tlast, m_eth0_tlast}), 219 .m_axis_tvalid ({xb_to_ep5_tvalid, xb_to_ep4_tvalid, xb_to_ep3_tvalid, xb_to_ep2_tvalid, xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid, m_eth1_tvalid, m_eth0_tvalid}), 220 .m_axis_tready ({xb_to_ep5_tready, xb_to_ep4_tready, xb_to_ep3_tready, xb_to_ep2_tready, xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready, m_eth1_tready, m_eth0_tready}), 221 .ext_rtcfg_stb (1'h0), 222 .ext_rtcfg_addr (16'h0), 223 .ext_rtcfg_data (32'h0), 224 .ext_rtcfg_ack () 225 ); 226 227 // ---------------------------------------------------- 228 // Stream Endpoints 229 // ---------------------------------------------------- 230 231 wire [CHDR_W-1:0] m_ep0_out0_tdata; 232 wire m_ep0_out0_tlast; 233 wire m_ep0_out0_tvalid; 234 wire m_ep0_out0_tready; 235 wire [CHDR_W-1:0] s_ep0_in0_tdata; 236 wire s_ep0_in0_tlast; 237 wire s_ep0_in0_tvalid; 238 wire s_ep0_in0_tready; 239 wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; 240 wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; 241 wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; 242 wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; 243 244 chdr_stream_endpoint #( 245 .PROTOVER (PROTOVER), 246 .CHDR_W (CHDR_W), 247 .AXIS_CTRL_EN (1), 248 .AXIS_DATA_EN (1), 249 .NUM_DATA_I (1), 250 .NUM_DATA_O (1), 251 .INST_NUM (0), 252 .CTRL_XBAR_PORT (1), 253 .INGRESS_BUFF_SIZE (14), 254 .MTU (MTU), 255 .REPORT_STRM_ERRS (1) 256 ) ep0_i ( 257 .rfnoc_chdr_clk (rfnoc_chdr_clk ), 258 .rfnoc_chdr_rst (rfnoc_chdr_rst ), 259 .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), 260 .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), 261 .device_id (device_id ), 262 .s_axis_chdr_tdata (xb_to_ep0_tdata ), 263 .s_axis_chdr_tlast (xb_to_ep0_tlast ), 264 .s_axis_chdr_tvalid (xb_to_ep0_tvalid ), 265 .s_axis_chdr_tready (xb_to_ep0_tready ), 266 .m_axis_chdr_tdata (ep0_to_xb_tdata ), 267 .m_axis_chdr_tlast (ep0_to_xb_tlast ), 268 .m_axis_chdr_tvalid (ep0_to_xb_tvalid ), 269 .m_axis_chdr_tready (ep0_to_xb_tready ), 270 .s_axis_data_tdata ({s_ep0_in0_tdata}), 271 .s_axis_data_tlast ({s_ep0_in0_tlast}), 272 .s_axis_data_tvalid ({s_ep0_in0_tvalid}), 273 .s_axis_data_tready ({s_ep0_in0_tready}), 274 .m_axis_data_tdata ({m_ep0_out0_tdata}), 275 .m_axis_data_tlast ({m_ep0_out0_tlast}), 276 .m_axis_data_tvalid ({m_ep0_out0_tvalid}), 277 .m_axis_data_tready ({m_ep0_out0_tready}), 278 .s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), 279 .s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), 280 .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), 281 .s_axis_ctrl_tready (s_ep0_ctrl_tready), 282 .m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), 283 .m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), 284 .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), 285 .m_axis_ctrl_tready (m_ep0_ctrl_tready), 286 .strm_seq_err_stb ( ), 287 .strm_data_err_stb ( ), 288 .strm_route_err_stb ( ), 289 .signal_data_err (1'b0 ) 290 ); 291 292 wire [CHDR_W-1:0] m_ep1_out0_tdata; 293 wire m_ep1_out0_tlast; 294 wire m_ep1_out0_tvalid; 295 wire m_ep1_out0_tready; 296 wire [CHDR_W-1:0] s_ep1_in0_tdata; 297 wire s_ep1_in0_tlast; 298 wire s_ep1_in0_tvalid; 299 wire s_ep1_in0_tready; 300 wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; 301 wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; 302 wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; 303 wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; 304 305 chdr_stream_endpoint #( 306 .PROTOVER (PROTOVER), 307 .CHDR_W (CHDR_W), 308 .AXIS_CTRL_EN (0), 309 .AXIS_DATA_EN (1), 310 .NUM_DATA_I (1), 311 .NUM_DATA_O (1), 312 .INST_NUM (1), 313 .CTRL_XBAR_PORT (2), 314 .INGRESS_BUFF_SIZE (14), 315 .MTU (MTU), 316 .REPORT_STRM_ERRS (1) 317 ) ep1_i ( 318 .rfnoc_chdr_clk (rfnoc_chdr_clk ), 319 .rfnoc_chdr_rst (rfnoc_chdr_rst ), 320 .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), 321 .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), 322 .device_id (device_id ), 323 .s_axis_chdr_tdata (xb_to_ep1_tdata ), 324 .s_axis_chdr_tlast (xb_to_ep1_tlast ), 325 .s_axis_chdr_tvalid (xb_to_ep1_tvalid ), 326 .s_axis_chdr_tready (xb_to_ep1_tready ), 327 .m_axis_chdr_tdata (ep1_to_xb_tdata ), 328 .m_axis_chdr_tlast (ep1_to_xb_tlast ), 329 .m_axis_chdr_tvalid (ep1_to_xb_tvalid ), 330 .m_axis_chdr_tready (ep1_to_xb_tready ), 331 .s_axis_data_tdata ({s_ep1_in0_tdata}), 332 .s_axis_data_tlast ({s_ep1_in0_tlast}), 333 .s_axis_data_tvalid ({s_ep1_in0_tvalid}), 334 .s_axis_data_tready ({s_ep1_in0_tready}), 335 .m_axis_data_tdata ({m_ep1_out0_tdata}), 336 .m_axis_data_tlast ({m_ep1_out0_tlast}), 337 .m_axis_data_tvalid ({m_ep1_out0_tvalid}), 338 .m_axis_data_tready ({m_ep1_out0_tready}), 339 .s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), 340 .s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), 341 .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), 342 .s_axis_ctrl_tready (s_ep1_ctrl_tready), 343 .m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), 344 .m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), 345 .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), 346 .m_axis_ctrl_tready (m_ep1_ctrl_tready), 347 .strm_seq_err_stb ( ), 348 .strm_data_err_stb ( ), 349 .strm_route_err_stb ( ), 350 .signal_data_err (1'b0 ) 351 ); 352 353 wire [CHDR_W-1:0] m_ep2_out0_tdata; 354 wire m_ep2_out0_tlast; 355 wire m_ep2_out0_tvalid; 356 wire m_ep2_out0_tready; 357 wire [CHDR_W-1:0] s_ep2_in0_tdata; 358 wire s_ep2_in0_tlast; 359 wire s_ep2_in0_tvalid; 360 wire s_ep2_in0_tready; 361 wire [31:0] m_ep2_ctrl_tdata , s_ep2_ctrl_tdata ; 362 wire m_ep2_ctrl_tlast , s_ep2_ctrl_tlast ; 363 wire m_ep2_ctrl_tvalid, s_ep2_ctrl_tvalid; 364 wire m_ep2_ctrl_tready, s_ep2_ctrl_tready; 365 366 chdr_stream_endpoint #( 367 .PROTOVER (PROTOVER), 368 .CHDR_W (CHDR_W), 369 .AXIS_CTRL_EN (0), 370 .AXIS_DATA_EN (1), 371 .NUM_DATA_I (1), 372 .NUM_DATA_O (1), 373 .INST_NUM (2), 374 .CTRL_XBAR_PORT (3), 375 .INGRESS_BUFF_SIZE (14), 376 .MTU (MTU), 377 .REPORT_STRM_ERRS (1) 378 ) ep2_i ( 379 .rfnoc_chdr_clk (rfnoc_chdr_clk ), 380 .rfnoc_chdr_rst (rfnoc_chdr_rst ), 381 .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), 382 .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), 383 .device_id (device_id ), 384 .s_axis_chdr_tdata (xb_to_ep2_tdata ), 385 .s_axis_chdr_tlast (xb_to_ep2_tlast ), 386 .s_axis_chdr_tvalid (xb_to_ep2_tvalid ), 387 .s_axis_chdr_tready (xb_to_ep2_tready ), 388 .m_axis_chdr_tdata (ep2_to_xb_tdata ), 389 .m_axis_chdr_tlast (ep2_to_xb_tlast ), 390 .m_axis_chdr_tvalid (ep2_to_xb_tvalid ), 391 .m_axis_chdr_tready (ep2_to_xb_tready ), 392 .s_axis_data_tdata ({s_ep2_in0_tdata}), 393 .s_axis_data_tlast ({s_ep2_in0_tlast}), 394 .s_axis_data_tvalid ({s_ep2_in0_tvalid}), 395 .s_axis_data_tready ({s_ep2_in0_tready}), 396 .m_axis_data_tdata ({m_ep2_out0_tdata}), 397 .m_axis_data_tlast ({m_ep2_out0_tlast}), 398 .m_axis_data_tvalid ({m_ep2_out0_tvalid}), 399 .m_axis_data_tready ({m_ep2_out0_tready}), 400 .s_axis_ctrl_tdata (s_ep2_ctrl_tdata ), 401 .s_axis_ctrl_tlast (s_ep2_ctrl_tlast ), 402 .s_axis_ctrl_tvalid (s_ep2_ctrl_tvalid), 403 .s_axis_ctrl_tready (s_ep2_ctrl_tready), 404 .m_axis_ctrl_tdata (m_ep2_ctrl_tdata ), 405 .m_axis_ctrl_tlast (m_ep2_ctrl_tlast ), 406 .m_axis_ctrl_tvalid (m_ep2_ctrl_tvalid), 407 .m_axis_ctrl_tready (m_ep2_ctrl_tready), 408 .strm_seq_err_stb ( ), 409 .strm_data_err_stb ( ), 410 .strm_route_err_stb ( ), 411 .signal_data_err (1'b0 ) 412 ); 413 414 wire [CHDR_W-1:0] m_ep3_out0_tdata; 415 wire m_ep3_out0_tlast; 416 wire m_ep3_out0_tvalid; 417 wire m_ep3_out0_tready; 418 wire [CHDR_W-1:0] s_ep3_in0_tdata; 419 wire s_ep3_in0_tlast; 420 wire s_ep3_in0_tvalid; 421 wire s_ep3_in0_tready; 422 wire [31:0] m_ep3_ctrl_tdata , s_ep3_ctrl_tdata ; 423 wire m_ep3_ctrl_tlast , s_ep3_ctrl_tlast ; 424 wire m_ep3_ctrl_tvalid, s_ep3_ctrl_tvalid; 425 wire m_ep3_ctrl_tready, s_ep3_ctrl_tready; 426 427 chdr_stream_endpoint #( 428 .PROTOVER (PROTOVER), 429 .CHDR_W (CHDR_W), 430 .AXIS_CTRL_EN (0), 431 .AXIS_DATA_EN (1), 432 .NUM_DATA_I (1), 433 .NUM_DATA_O (1), 434 .INST_NUM (3), 435 .CTRL_XBAR_PORT (4), 436 .INGRESS_BUFF_SIZE (14), 437 .MTU (MTU), 438 .REPORT_STRM_ERRS (1) 439 ) ep3_i ( 440 .rfnoc_chdr_clk (rfnoc_chdr_clk ), 441 .rfnoc_chdr_rst (rfnoc_chdr_rst ), 442 .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), 443 .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), 444 .device_id (device_id ), 445 .s_axis_chdr_tdata (xb_to_ep3_tdata ), 446 .s_axis_chdr_tlast (xb_to_ep3_tlast ), 447 .s_axis_chdr_tvalid (xb_to_ep3_tvalid ), 448 .s_axis_chdr_tready (xb_to_ep3_tready ), 449 .m_axis_chdr_tdata (ep3_to_xb_tdata ), 450 .m_axis_chdr_tlast (ep3_to_xb_tlast ), 451 .m_axis_chdr_tvalid (ep3_to_xb_tvalid ), 452 .m_axis_chdr_tready (ep3_to_xb_tready ), 453 .s_axis_data_tdata ({s_ep3_in0_tdata}), 454 .s_axis_data_tlast ({s_ep3_in0_tlast}), 455 .s_axis_data_tvalid ({s_ep3_in0_tvalid}), 456 .s_axis_data_tready ({s_ep3_in0_tready}), 457 .m_axis_data_tdata ({m_ep3_out0_tdata}), 458 .m_axis_data_tlast ({m_ep3_out0_tlast}), 459 .m_axis_data_tvalid ({m_ep3_out0_tvalid}), 460 .m_axis_data_tready ({m_ep3_out0_tready}), 461 .s_axis_ctrl_tdata (s_ep3_ctrl_tdata ), 462 .s_axis_ctrl_tlast (s_ep3_ctrl_tlast ), 463 .s_axis_ctrl_tvalid (s_ep3_ctrl_tvalid), 464 .s_axis_ctrl_tready (s_ep3_ctrl_tready), 465 .m_axis_ctrl_tdata (m_ep3_ctrl_tdata ), 466 .m_axis_ctrl_tlast (m_ep3_ctrl_tlast ), 467 .m_axis_ctrl_tvalid (m_ep3_ctrl_tvalid), 468 .m_axis_ctrl_tready (m_ep3_ctrl_tready), 469 .strm_seq_err_stb ( ), 470 .strm_data_err_stb ( ), 471 .strm_route_err_stb ( ), 472 .signal_data_err (1'b0 ) 473 ); 474 475 wire [CHDR_W-1:0] m_ep4_out0_tdata; 476 wire m_ep4_out0_tlast; 477 wire m_ep4_out0_tvalid; 478 wire m_ep4_out0_tready; 479 wire [CHDR_W-1:0] s_ep4_in0_tdata; 480 wire s_ep4_in0_tlast; 481 wire s_ep4_in0_tvalid; 482 wire s_ep4_in0_tready; 483 wire [31:0] m_ep4_ctrl_tdata , s_ep4_ctrl_tdata ; 484 wire m_ep4_ctrl_tlast , s_ep4_ctrl_tlast ; 485 wire m_ep4_ctrl_tvalid, s_ep4_ctrl_tvalid; 486 wire m_ep4_ctrl_tready, s_ep4_ctrl_tready; 487 488 chdr_stream_endpoint #( 489 .PROTOVER (PROTOVER), 490 .CHDR_W (CHDR_W), 491 .AXIS_CTRL_EN (0), 492 .AXIS_DATA_EN (1), 493 .NUM_DATA_I (1), 494 .NUM_DATA_O (1), 495 .INST_NUM (4), 496 .CTRL_XBAR_PORT (5), 497 .INGRESS_BUFF_SIZE (14), 498 .MTU (MTU), 499 .REPORT_STRM_ERRS (1) 500 ) ep4_i ( 501 .rfnoc_chdr_clk (rfnoc_chdr_clk ), 502 .rfnoc_chdr_rst (rfnoc_chdr_rst ), 503 .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), 504 .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), 505 .device_id (device_id ), 506 .s_axis_chdr_tdata (xb_to_ep4_tdata ), 507 .s_axis_chdr_tlast (xb_to_ep4_tlast ), 508 .s_axis_chdr_tvalid (xb_to_ep4_tvalid ), 509 .s_axis_chdr_tready (xb_to_ep4_tready ), 510 .m_axis_chdr_tdata (ep4_to_xb_tdata ), 511 .m_axis_chdr_tlast (ep4_to_xb_tlast ), 512 .m_axis_chdr_tvalid (ep4_to_xb_tvalid ), 513 .m_axis_chdr_tready (ep4_to_xb_tready ), 514 .s_axis_data_tdata ({s_ep4_in0_tdata}), 515 .s_axis_data_tlast ({s_ep4_in0_tlast}), 516 .s_axis_data_tvalid ({s_ep4_in0_tvalid}), 517 .s_axis_data_tready ({s_ep4_in0_tready}), 518 .m_axis_data_tdata ({m_ep4_out0_tdata}), 519 .m_axis_data_tlast ({m_ep4_out0_tlast}), 520 .m_axis_data_tvalid ({m_ep4_out0_tvalid}), 521 .m_axis_data_tready ({m_ep4_out0_tready}), 522 .s_axis_ctrl_tdata (s_ep4_ctrl_tdata ), 523 .s_axis_ctrl_tlast (s_ep4_ctrl_tlast ), 524 .s_axis_ctrl_tvalid (s_ep4_ctrl_tvalid), 525 .s_axis_ctrl_tready (s_ep4_ctrl_tready), 526 .m_axis_ctrl_tdata (m_ep4_ctrl_tdata ), 527 .m_axis_ctrl_tlast (m_ep4_ctrl_tlast ), 528 .m_axis_ctrl_tvalid (m_ep4_ctrl_tvalid), 529 .m_axis_ctrl_tready (m_ep4_ctrl_tready), 530 .strm_seq_err_stb ( ), 531 .strm_data_err_stb ( ), 532 .strm_route_err_stb ( ), 533 .signal_data_err (1'b0 ) 534 ); 535 536 wire [CHDR_W-1:0] m_ep5_out0_tdata; 537 wire m_ep5_out0_tlast; 538 wire m_ep5_out0_tvalid; 539 wire m_ep5_out0_tready; 540 wire [CHDR_W-1:0] s_ep5_in0_tdata; 541 wire s_ep5_in0_tlast; 542 wire s_ep5_in0_tvalid; 543 wire s_ep5_in0_tready; 544 wire [31:0] m_ep5_ctrl_tdata , s_ep5_ctrl_tdata ; 545 wire m_ep5_ctrl_tlast , s_ep5_ctrl_tlast ; 546 wire m_ep5_ctrl_tvalid, s_ep5_ctrl_tvalid; 547 wire m_ep5_ctrl_tready, s_ep5_ctrl_tready; 548 549 chdr_stream_endpoint #( 550 .PROTOVER (PROTOVER), 551 .CHDR_W (CHDR_W), 552 .AXIS_CTRL_EN (0), 553 .AXIS_DATA_EN (1), 554 .NUM_DATA_I (1), 555 .NUM_DATA_O (1), 556 .INST_NUM (5), 557 .CTRL_XBAR_PORT (6), 558 .INGRESS_BUFF_SIZE (14), 559 .MTU (MTU), 560 .REPORT_STRM_ERRS (1) 561 ) ep5_i ( 562 .rfnoc_chdr_clk (rfnoc_chdr_clk ), 563 .rfnoc_chdr_rst (rfnoc_chdr_rst ), 564 .rfnoc_ctrl_clk (rfnoc_ctrl_clk ), 565 .rfnoc_ctrl_rst (rfnoc_ctrl_rst ), 566 .device_id (device_id ), 567 .s_axis_chdr_tdata (xb_to_ep5_tdata ), 568 .s_axis_chdr_tlast (xb_to_ep5_tlast ), 569 .s_axis_chdr_tvalid (xb_to_ep5_tvalid ), 570 .s_axis_chdr_tready (xb_to_ep5_tready ), 571 .m_axis_chdr_tdata (ep5_to_xb_tdata ), 572 .m_axis_chdr_tlast (ep5_to_xb_tlast ), 573 .m_axis_chdr_tvalid (ep5_to_xb_tvalid ), 574 .m_axis_chdr_tready (ep5_to_xb_tready ), 575 .s_axis_data_tdata ({s_ep5_in0_tdata}), 576 .s_axis_data_tlast ({s_ep5_in0_tlast}), 577 .s_axis_data_tvalid ({s_ep5_in0_tvalid}), 578 .s_axis_data_tready ({s_ep5_in0_tready}), 579 .m_axis_data_tdata ({m_ep5_out0_tdata}), 580 .m_axis_data_tlast ({m_ep5_out0_tlast}), 581 .m_axis_data_tvalid ({m_ep5_out0_tvalid}), 582 .m_axis_data_tready ({m_ep5_out0_tready}), 583 .s_axis_ctrl_tdata (s_ep5_ctrl_tdata ), 584 .s_axis_ctrl_tlast (s_ep5_ctrl_tlast ), 585 .s_axis_ctrl_tvalid (s_ep5_ctrl_tvalid), 586 .s_axis_ctrl_tready (s_ep5_ctrl_tready), 587 .m_axis_ctrl_tdata (m_ep5_ctrl_tdata ), 588 .m_axis_ctrl_tlast (m_ep5_ctrl_tlast ), 589 .m_axis_ctrl_tvalid (m_ep5_ctrl_tvalid), 590 .m_axis_ctrl_tready (m_ep5_ctrl_tready), 591 .strm_seq_err_stb ( ), 592 .strm_data_err_stb ( ), 593 .strm_route_err_stb ( ), 594 .signal_data_err (1'b0 ) 595 ); 596 597 598 599 // ---------------------------------------------------- 600 // Control Crossbar 601 // ---------------------------------------------------- 602 603 wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; 604 wire m_core_ctrl_tlast , s_core_ctrl_tlast ; 605 wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; 606 wire m_core_ctrl_tready, s_core_ctrl_tready; 607 wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; 608 wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; 609 wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; 610 wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; 611 wire [31:0] m_radio1_ctrl_tdata , s_radio1_ctrl_tdata ; 612 wire m_radio1_ctrl_tlast , s_radio1_ctrl_tlast ; 613 wire m_radio1_ctrl_tvalid, s_radio1_ctrl_tvalid; 614 wire m_radio1_ctrl_tready, s_radio1_ctrl_tready; 615 wire [31:0] m_fifo0_ctrl_tdata , s_fifo0_ctrl_tdata ; 616 wire m_fifo0_ctrl_tlast , s_fifo0_ctrl_tlast ; 617 wire m_fifo0_ctrl_tvalid, s_fifo0_ctrl_tvalid; 618 wire m_fifo0_ctrl_tready, s_fifo0_ctrl_tready; 619 620 axis_ctrl_crossbar_nxn #( 621 .WIDTH (32), 622 .NPORTS (5), 623 .TOPOLOGY ("TORUS"), 624 .INGRESS_BUFF_SIZE(5), 625 .ROUTER_BUFF_SIZE (5), 626 .ROUTING_ALLOC ("WORMHOLE"), 627 .SWITCH_ALLOC ("PRIO") 628 ) ctrl_xb_i ( 629 .clk (rfnoc_ctrl_clk), 630 .reset (rfnoc_ctrl_rst), 631 .s_axis_tdata ({m_fifo0_ctrl_tdata , m_radio1_ctrl_tdata , m_radio0_ctrl_tdata , m_ep0_ctrl_tdata , m_core_ctrl_tdata }), 632 .s_axis_tvalid ({m_fifo0_ctrl_tvalid, m_radio1_ctrl_tvalid, m_radio0_ctrl_tvalid, m_ep0_ctrl_tvalid, m_core_ctrl_tvalid}), 633 .s_axis_tlast ({m_fifo0_ctrl_tlast , m_radio1_ctrl_tlast , m_radio0_ctrl_tlast , m_ep0_ctrl_tlast , m_core_ctrl_tlast }), 634 .s_axis_tready ({m_fifo0_ctrl_tready, m_radio1_ctrl_tready, m_radio0_ctrl_tready, m_ep0_ctrl_tready, m_core_ctrl_tready}), 635 .m_axis_tdata ({s_fifo0_ctrl_tdata , s_radio1_ctrl_tdata , s_radio0_ctrl_tdata , s_ep0_ctrl_tdata , s_core_ctrl_tdata }), 636 .m_axis_tvalid ({s_fifo0_ctrl_tvalid, s_radio1_ctrl_tvalid, s_radio0_ctrl_tvalid, s_ep0_ctrl_tvalid, s_core_ctrl_tvalid}), 637 .m_axis_tlast ({s_fifo0_ctrl_tlast , s_radio1_ctrl_tlast , s_radio0_ctrl_tlast , s_ep0_ctrl_tlast , s_core_ctrl_tlast }), 638 .m_axis_tready ({s_fifo0_ctrl_tready, s_radio1_ctrl_tready, s_radio0_ctrl_tready, s_ep0_ctrl_tready, s_core_ctrl_tready}), 639 .deadlock_detected() 640 ); 641 642 // ---------------------------------------------------- 643 // RFNoC Core Kernel 644 // ---------------------------------------------------- 645 wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; 646 647 rfnoc_core_kernel #( 648 .PROTOVER (PROTOVER), 649 .DEVICE_TYPE (16'h1300), 650 .DEVICE_FAMILY ("7SERIES"), 651 .SAFE_START_CLKS (0), 652 .NUM_BLOCKS (3), 653 .NUM_STREAM_ENDPOINTS(6), 654 .NUM_ENDPOINTS_CTRL (1), 655 .NUM_TRANSPORTS (3), 656 .NUM_EDGES (12), 657 .CHDR_XBAR_PRESENT (1), 658 .EDGE_TBL_FILE (EDGE_TBL_FILE) 659 ) core_kernel_i ( 660 .chdr_aclk (chdr_aclk), 661 .chdr_aclk_locked (1'b1), 662 .ctrl_aclk (ctrl_aclk), 663 .ctrl_aclk_locked (1'b1), 664 .core_arst (core_arst), 665 .core_chdr_clk (rfnoc_chdr_clk), 666 .core_chdr_rst (rfnoc_chdr_rst), 667 .core_ctrl_clk (rfnoc_ctrl_clk), 668 .core_ctrl_rst (rfnoc_ctrl_rst), 669 .s_axis_ctrl_tdata (s_core_ctrl_tdata ), 670 .s_axis_ctrl_tlast (s_core_ctrl_tlast ), 671 .s_axis_ctrl_tvalid (s_core_ctrl_tvalid), 672 .s_axis_ctrl_tready (s_core_ctrl_tready), 673 .m_axis_ctrl_tdata (m_core_ctrl_tdata ), 674 .m_axis_ctrl_tlast (m_core_ctrl_tlast ), 675 .m_axis_ctrl_tvalid (m_core_ctrl_tvalid), 676 .m_axis_ctrl_tready (m_core_ctrl_tready), 677 .device_id (device_id), 678 .rfnoc_core_config (rfnoc_core_config), 679 .rfnoc_core_status (rfnoc_core_status) 680 ); 681 682 // ---------------------------------------------------- 683 // Blocks 684 // ---------------------------------------------------- 685 686 // ---------------------------------------------------- 687 // radio0 688 // ---------------------------------------------------- 689 wire radio0_radio_clk; 690 wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; 691 wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; 692 wire s_radio0_in_1_tvalid, s_radio0_in_0_tvalid; 693 wire s_radio0_in_1_tready, s_radio0_in_0_tready; 694 wire [CHDR_W-1:0] m_radio0_out_1_tdata , m_radio0_out_0_tdata ; 695 wire m_radio0_out_1_tlast , m_radio0_out_0_tlast ; 696 wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; 697 wire m_radio0_out_1_tready, m_radio0_out_0_tready; 698 699 // ctrl_port 700 wire [ 1-1:0] radio0_m_ctrlport_req_wr; 701 wire [ 1-1:0] radio0_m_ctrlport_req_rd; 702 wire [ 20-1:0] radio0_m_ctrlport_req_addr; 703 wire [ 32-1:0] radio0_m_ctrlport_req_data; 704 wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; 705 wire [ 1-1:0] radio0_m_ctrlport_req_has_time; 706 wire [ 64-1:0] radio0_m_ctrlport_req_time; 707 wire [ 1-1:0] radio0_m_ctrlport_resp_ack; 708 wire [ 2-1:0] radio0_m_ctrlport_resp_status; 709 wire [ 32-1:0] radio0_m_ctrlport_resp_data; 710 // time_keeper 711 wire [ 64-1:0] radio0_radio_time; 712 // x300_radio 713 wire [ 64-1:0] radio0_radio_rx_data; 714 wire [ 2-1:0] radio0_radio_rx_stb; 715 wire [ 2-1:0] radio0_radio_rx_running; 716 wire [ 64-1:0] radio0_radio_tx_data; 717 wire [ 2-1:0] radio0_radio_tx_stb; 718 wire [ 2-1:0] radio0_radio_tx_running; 719 720 rfnoc_block_radio #( 721 .THIS_PORTID(2), 722 .CHDR_W(CHDR_W), 723 .NUM_PORTS(2), 724 .MTU(MTU) 725 ) b_radio0_0 ( 726 .rfnoc_chdr_clk (rfnoc_chdr_clk), 727 .rfnoc_ctrl_clk (rfnoc_ctrl_clk), 728 .radio_clk(radio0_radio_clk), 729 .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), 730 .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), 731 732 .m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), 733 .m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), 734 .m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), 735 .m_ctrlport_req_data(radio0_m_ctrlport_req_data), 736 .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), 737 .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), 738 .m_ctrlport_req_time(radio0_m_ctrlport_req_time), 739 .m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), 740 .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), 741 .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), 742 .radio_time(radio0_radio_time), 743 .radio_rx_data(radio0_radio_rx_data), 744 .radio_rx_stb(radio0_radio_rx_stb), 745 .radio_rx_running(radio0_radio_rx_running), 746 .radio_tx_data(radio0_radio_tx_data), 747 .radio_tx_stb(radio0_radio_tx_stb), 748 .radio_tx_running(radio0_radio_tx_running), 749 750 .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), 751 .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), 752 .s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), 753 .s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), 754 .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), 755 .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), 756 .m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), 757 .m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), 758 .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), 759 .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), 760 .s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), 761 .s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), 762 .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), 763 .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), 764 .m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), 765 .m_rfnoc_ctrl_tready(m_radio0_ctrl_tready) 766 ); 767 768 769 // ---------------------------------------------------- 770 // radio1 771 // ---------------------------------------------------- 772 wire radio1_radio_clk; 773 wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; 774 wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; 775 wire s_radio1_in_1_tvalid, s_radio1_in_0_tvalid; 776 wire s_radio1_in_1_tready, s_radio1_in_0_tready; 777 wire [CHDR_W-1:0] m_radio1_out_1_tdata , m_radio1_out_0_tdata ; 778 wire m_radio1_out_1_tlast , m_radio1_out_0_tlast ; 779 wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid; 780 wire m_radio1_out_1_tready, m_radio1_out_0_tready; 781 782 // ctrl_port 783 wire [ 1-1:0] radio1_m_ctrlport_req_wr; 784 wire [ 1-1:0] radio1_m_ctrlport_req_rd; 785 wire [ 20-1:0] radio1_m_ctrlport_req_addr; 786 wire [ 32-1:0] radio1_m_ctrlport_req_data; 787 wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; 788 wire [ 1-1:0] radio1_m_ctrlport_req_has_time; 789 wire [ 64-1:0] radio1_m_ctrlport_req_time; 790 wire [ 1-1:0] radio1_m_ctrlport_resp_ack; 791 wire [ 2-1:0] radio1_m_ctrlport_resp_status; 792 wire [ 32-1:0] radio1_m_ctrlport_resp_data; 793 // time_keeper 794 wire [ 64-1:0] radio1_radio_time; 795 // x300_radio 796 wire [ 64-1:0] radio1_radio_rx_data; 797 wire [ 2-1:0] radio1_radio_rx_stb; 798 wire [ 2-1:0] radio1_radio_rx_running; 799 wire [ 64-1:0] radio1_radio_tx_data; 800 wire [ 2-1:0] radio1_radio_tx_stb; 801 wire [ 2-1:0] radio1_radio_tx_running; 802 803 rfnoc_block_radio #( 804 .THIS_PORTID(3), 805 .CHDR_W(CHDR_W), 806 .NUM_PORTS(2), 807 .MTU(MTU) 808 ) b_radio1_1 ( 809 .rfnoc_chdr_clk (rfnoc_chdr_clk), 810 .rfnoc_ctrl_clk (rfnoc_ctrl_clk), 811 .radio_clk(radio1_radio_clk), 812 .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), 813 .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), 814 815 .m_ctrlport_req_wr(radio1_m_ctrlport_req_wr), 816 .m_ctrlport_req_rd(radio1_m_ctrlport_req_rd), 817 .m_ctrlport_req_addr(radio1_m_ctrlport_req_addr), 818 .m_ctrlport_req_data(radio1_m_ctrlport_req_data), 819 .m_ctrlport_req_byte_en(radio1_m_ctrlport_req_byte_en), 820 .m_ctrlport_req_has_time(radio1_m_ctrlport_req_has_time), 821 .m_ctrlport_req_time(radio1_m_ctrlport_req_time), 822 .m_ctrlport_resp_ack(radio1_m_ctrlport_resp_ack), 823 .m_ctrlport_resp_status(radio1_m_ctrlport_resp_status), 824 .m_ctrlport_resp_data(radio1_m_ctrlport_resp_data), 825 .radio_time(radio1_radio_time), 826 .radio_rx_data(radio1_radio_rx_data), 827 .radio_rx_stb(radio1_radio_rx_stb), 828 .radio_rx_running(radio1_radio_rx_running), 829 .radio_tx_data(radio1_radio_tx_data), 830 .radio_tx_stb(radio1_radio_tx_stb), 831 .radio_tx_running(radio1_radio_tx_running), 832 833 .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), 834 .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), 835 .s_rfnoc_chdr_tvalid({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), 836 .s_rfnoc_chdr_tready({s_radio1_in_1_tready, s_radio1_in_0_tready}), 837 .m_rfnoc_chdr_tdata ({m_radio1_out_1_tdata , m_radio1_out_0_tdata }), 838 .m_rfnoc_chdr_tlast ({m_radio1_out_1_tlast , m_radio1_out_0_tlast }), 839 .m_rfnoc_chdr_tvalid({m_radio1_out_1_tvalid, m_radio1_out_0_tvalid}), 840 .m_rfnoc_chdr_tready({m_radio1_out_1_tready, m_radio1_out_0_tready}), 841 .s_rfnoc_ctrl_tdata (s_radio1_ctrl_tdata ), 842 .s_rfnoc_ctrl_tlast (s_radio1_ctrl_tlast ), 843 .s_rfnoc_ctrl_tvalid(s_radio1_ctrl_tvalid), 844 .s_rfnoc_ctrl_tready(s_radio1_ctrl_tready), 845 .m_rfnoc_ctrl_tdata (m_radio1_ctrl_tdata ), 846 .m_rfnoc_ctrl_tlast (m_radio1_ctrl_tlast ), 847 .m_rfnoc_ctrl_tvalid(m_radio1_ctrl_tvalid), 848 .m_rfnoc_ctrl_tready(m_radio1_ctrl_tready) 849 ); 850 851 852 // ---------------------------------------------------- 853 // fifo0 854 // ---------------------------------------------------- 855 wire fifo0_mem_clk; 856 wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; 857 wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; 858 wire s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid; 859 wire s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready; 860 wire [CHDR_W-1:0] m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata ; 861 wire m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast ; 862 wire m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid; 863 wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; 864 865 // axi_ram 866 wire [ 1-1:0] fifo0_axi_rst; 867 wire [ 4-1:0] fifo0_m_axi_awid; 868 wire [128-1:0] fifo0_m_axi_awaddr; 869 wire [ 32-1:0] fifo0_m_axi_awlen; 870 wire [ 12-1:0] fifo0_m_axi_awsize; 871 wire [ 8-1:0] fifo0_m_axi_awburst; 872 wire [ 4-1:0] fifo0_m_axi_awlock; 873 wire [ 16-1:0] fifo0_m_axi_awcache; 874 wire [ 12-1:0] fifo0_m_axi_awprot; 875 wire [ 16-1:0] fifo0_m_axi_awqos; 876 wire [ 16-1:0] fifo0_m_axi_awregion; 877 wire [ 4-1:0] fifo0_m_axi_awuser; 878 wire [ 4-1:0] fifo0_m_axi_awvalid; 879 wire [ 4-1:0] fifo0_m_axi_awready; 880 wire [256-1:0] fifo0_m_axi_wdata; 881 wire [ 32-1:0] fifo0_m_axi_wstrb; 882 wire [ 4-1:0] fifo0_m_axi_wlast; 883 wire [ 4-1:0] fifo0_m_axi_wuser; 884 wire [ 4-1:0] fifo0_m_axi_wvalid; 885 wire [ 4-1:0] fifo0_m_axi_wready; 886 wire [ 4-1:0] fifo0_m_axi_bid; 887 wire [ 8-1:0] fifo0_m_axi_bresp; 888 wire [ 4-1:0] fifo0_m_axi_buser; 889 wire [ 4-1:0] fifo0_m_axi_bvalid; 890 wire [ 4-1:0] fifo0_m_axi_bready; 891 wire [ 4-1:0] fifo0_m_axi_arid; 892 wire [128-1:0] fifo0_m_axi_araddr; 893 wire [ 32-1:0] fifo0_m_axi_arlen; 894 wire [ 12-1:0] fifo0_m_axi_arsize; 895 wire [ 8-1:0] fifo0_m_axi_arburst; 896 wire [ 4-1:0] fifo0_m_axi_arlock; 897 wire [ 16-1:0] fifo0_m_axi_arcache; 898 wire [ 12-1:0] fifo0_m_axi_arprot; 899 wire [ 16-1:0] fifo0_m_axi_arqos; 900 wire [ 16-1:0] fifo0_m_axi_arregion; 901 wire [ 4-1:0] fifo0_m_axi_aruser; 902 wire [ 4-1:0] fifo0_m_axi_arvalid; 903 wire [ 4-1:0] fifo0_m_axi_arready; 904 wire [ 4-1:0] fifo0_m_axi_rid; 905 wire [256-1:0] fifo0_m_axi_rdata; 906 wire [ 8-1:0] fifo0_m_axi_rresp; 907 wire [ 4-1:0] fifo0_m_axi_rlast; 908 wire [ 4-1:0] fifo0_m_axi_ruser; 909 wire [ 4-1:0] fifo0_m_axi_rvalid; 910 wire [ 4-1:0] fifo0_m_axi_rready; 911 912 rfnoc_block_axi_ram_fifo #( 913 .THIS_PORTID(4), 914 .CHDR_W(CHDR_W), 915 .NUM_PORTS(4), 916 .MEM_DATA_W(64), 917 .MEM_ADDR_W(31), 918 .FIFO_ADDR_BASE({30'h06000000, 30'h04000000, 30'h02000000, 30'h00000000}), 919 .FIFO_ADDR_MASK({30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF, 30'h01FFFFFF}), 920 .MEM_CLK_RATE(303819444), 921 .MTU(MTU) 922 ) b_fifo0_2 ( 923 .rfnoc_chdr_clk (rfnoc_chdr_clk), 924 .rfnoc_ctrl_clk (rfnoc_ctrl_clk), 925 .mem_clk(fifo0_mem_clk), 926 .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), 927 .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), 928 929 .axi_rst(fifo0_axi_rst), 930 .m_axi_awid(fifo0_m_axi_awid), 931 .m_axi_awaddr(fifo0_m_axi_awaddr), 932 .m_axi_awlen(fifo0_m_axi_awlen), 933 .m_axi_awsize(fifo0_m_axi_awsize), 934 .m_axi_awburst(fifo0_m_axi_awburst), 935 .m_axi_awlock(fifo0_m_axi_awlock), 936 .m_axi_awcache(fifo0_m_axi_awcache), 937 .m_axi_awprot(fifo0_m_axi_awprot), 938 .m_axi_awqos(fifo0_m_axi_awqos), 939 .m_axi_awregion(fifo0_m_axi_awregion), 940 .m_axi_awuser(fifo0_m_axi_awuser), 941 .m_axi_awvalid(fifo0_m_axi_awvalid), 942 .m_axi_awready(fifo0_m_axi_awready), 943 .m_axi_wdata(fifo0_m_axi_wdata), 944 .m_axi_wstrb(fifo0_m_axi_wstrb), 945 .m_axi_wlast(fifo0_m_axi_wlast), 946 .m_axi_wuser(fifo0_m_axi_wuser), 947 .m_axi_wvalid(fifo0_m_axi_wvalid), 948 .m_axi_wready(fifo0_m_axi_wready), 949 .m_axi_bid(fifo0_m_axi_bid), 950 .m_axi_bresp(fifo0_m_axi_bresp), 951 .m_axi_buser(fifo0_m_axi_buser), 952 .m_axi_bvalid(fifo0_m_axi_bvalid), 953 .m_axi_bready(fifo0_m_axi_bready), 954 .m_axi_arid(fifo0_m_axi_arid), 955 .m_axi_araddr(fifo0_m_axi_araddr), 956 .m_axi_arlen(fifo0_m_axi_arlen), 957 .m_axi_arsize(fifo0_m_axi_arsize), 958 .m_axi_arburst(fifo0_m_axi_arburst), 959 .m_axi_arlock(fifo0_m_axi_arlock), 960 .m_axi_arcache(fifo0_m_axi_arcache), 961 .m_axi_arprot(fifo0_m_axi_arprot), 962 .m_axi_arqos(fifo0_m_axi_arqos), 963 .m_axi_arregion(fifo0_m_axi_arregion), 964 .m_axi_aruser(fifo0_m_axi_aruser), 965 .m_axi_arvalid(fifo0_m_axi_arvalid), 966 .m_axi_arready(fifo0_m_axi_arready), 967 .m_axi_rid(fifo0_m_axi_rid), 968 .m_axi_rdata(fifo0_m_axi_rdata), 969 .m_axi_rresp(fifo0_m_axi_rresp), 970 .m_axi_rlast(fifo0_m_axi_rlast), 971 .m_axi_ruser(fifo0_m_axi_ruser), 972 .m_axi_rvalid(fifo0_m_axi_rvalid), 973 .m_axi_rready(fifo0_m_axi_rready), 974 975 .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), 976 .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), 977 .s_rfnoc_chdr_tvalid({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), 978 .s_rfnoc_chdr_tready({s_fifo0_in_3_tready, s_fifo0_in_2_tready, s_fifo0_in_1_tready, s_fifo0_in_0_tready}), 979 .m_rfnoc_chdr_tdata ({m_fifo0_out_3_tdata , m_fifo0_out_2_tdata , m_fifo0_out_1_tdata , m_fifo0_out_0_tdata }), 980 .m_rfnoc_chdr_tlast ({m_fifo0_out_3_tlast , m_fifo0_out_2_tlast , m_fifo0_out_1_tlast , m_fifo0_out_0_tlast }), 981 .m_rfnoc_chdr_tvalid({m_fifo0_out_3_tvalid, m_fifo0_out_2_tvalid, m_fifo0_out_1_tvalid, m_fifo0_out_0_tvalid}), 982 .m_rfnoc_chdr_tready({m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready}), 983 .s_rfnoc_ctrl_tdata (s_fifo0_ctrl_tdata ), 984 .s_rfnoc_ctrl_tlast (s_fifo0_ctrl_tlast ), 985 .s_rfnoc_ctrl_tvalid(s_fifo0_ctrl_tvalid), 986 .s_rfnoc_ctrl_tready(s_fifo0_ctrl_tready), 987 .m_rfnoc_ctrl_tdata (m_fifo0_ctrl_tdata ), 988 .m_rfnoc_ctrl_tlast (m_fifo0_ctrl_tlast ), 989 .m_rfnoc_ctrl_tvalid(m_fifo0_ctrl_tvalid), 990 .m_rfnoc_ctrl_tready(m_fifo0_ctrl_tready) 991 ); 992 993 994 // ---------------------------------------------------- 995 // Static Router 996 // ---------------------------------------------------- 997 assign s_radio0_in_0_tdata = m_ep0_out0_tdata ; 998 assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; 999 assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; 1000 assign m_ep0_out0_tready = s_radio0_in_0_tready; 1001 1002 assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; 1003 assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; 1004 assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; 1005 assign m_radio0_out_0_tready = s_ep0_in0_tready; 1006 1007 assign s_radio0_in_1_tdata = m_ep1_out0_tdata ; 1008 assign s_radio0_in_1_tlast = m_ep1_out0_tlast ; 1009 assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; 1010 assign m_ep1_out0_tready = s_radio0_in_1_tready; 1011 1012 assign s_ep1_in0_tdata = m_radio0_out_1_tdata ; 1013 assign s_ep1_in0_tlast = m_radio0_out_1_tlast ; 1014 assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; 1015 assign m_radio0_out_1_tready = s_ep1_in0_tready; 1016 1017 assign s_radio1_in_0_tdata = m_ep2_out0_tdata ; 1018 assign s_radio1_in_0_tlast = m_ep2_out0_tlast ; 1019 assign s_radio1_in_0_tvalid = m_ep2_out0_tvalid; 1020 assign m_ep2_out0_tready = s_radio1_in_0_tready; 1021 1022 assign s_ep2_in0_tdata = m_radio1_out_0_tdata ; 1023 assign s_ep2_in0_tlast = m_radio1_out_0_tlast ; 1024 assign s_ep2_in0_tvalid = m_radio1_out_0_tvalid; 1025 assign m_radio1_out_0_tready = s_ep2_in0_tready; 1026 1027 assign s_radio1_in_1_tdata = m_ep3_out0_tdata ; 1028 assign s_radio1_in_1_tlast = m_ep3_out0_tlast ; 1029 assign s_radio1_in_1_tvalid = m_ep3_out0_tvalid; 1030 assign m_ep3_out0_tready = s_radio1_in_1_tready; 1031 1032 assign s_ep3_in0_tdata = m_radio1_out_1_tdata ; 1033 assign s_ep3_in0_tlast = m_radio1_out_1_tlast ; 1034 assign s_ep3_in0_tvalid = m_radio1_out_1_tvalid; 1035 assign m_radio1_out_1_tready = s_ep3_in0_tready; 1036 1037 assign s_fifo0_in_0_tdata = m_ep4_out0_tdata ; 1038 assign s_fifo0_in_0_tlast = m_ep4_out0_tlast ; 1039 assign s_fifo0_in_0_tvalid = m_ep4_out0_tvalid; 1040 assign m_ep4_out0_tready = s_fifo0_in_0_tready; 1041 1042 assign s_ep4_in0_tdata = m_fifo0_out_0_tdata ; 1043 assign s_ep4_in0_tlast = m_fifo0_out_0_tlast ; 1044 assign s_ep4_in0_tvalid = m_fifo0_out_0_tvalid; 1045 assign m_fifo0_out_0_tready = s_ep4_in0_tready; 1046 1047 assign s_fifo0_in_1_tdata = m_ep5_out0_tdata ; 1048 assign s_fifo0_in_1_tlast = m_ep5_out0_tlast ; 1049 assign s_fifo0_in_1_tvalid = m_ep5_out0_tvalid; 1050 assign m_ep5_out0_tready = s_fifo0_in_1_tready; 1051 1052 assign s_ep5_in0_tdata = m_fifo0_out_1_tdata ; 1053 assign s_ep5_in0_tlast = m_fifo0_out_1_tlast ; 1054 assign s_ep5_in0_tvalid = m_fifo0_out_1_tvalid; 1055 assign m_fifo0_out_1_tready = s_ep5_in0_tready; 1056 1057 1058 // ---------------------------------------------------- 1059 // Unused Ports 1060 // ---------------------------------------------------- 1061 assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; 1062 assign s_fifo0_in_2_tlast = 1'b0; 1063 assign s_fifo0_in_2_tvalid = 1'b0; 1064 assign s_fifo0_in_3_tdata = {CHDR_W{1'b0}}; 1065 assign s_fifo0_in_3_tlast = 1'b0; 1066 assign s_fifo0_in_3_tvalid = 1'b0; 1067 assign m_fifo0_out_2_tready = 1'b1; 1068 assign m_fifo0_out_3_tready = 1'b1; 1069 1070 // ---------------------------------------------------- 1071 // Clock Domains 1072 // ---------------------------------------------------- 1073 assign radio0_radio_clk = radio_clk; 1074 assign radio1_radio_clk = radio_clk; 1075 assign fifo0_mem_clk = dram_clk; 1076 1077 1078 // ---------------------------------------------------- 1079 // IO Port Connection 1080 // ---------------------------------------------------- 1081 // Master/Slave Connections: 1082 assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; 1083 assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; 1084 assign m_ctrlport_radio0_req_addr = radio0_m_ctrlport_req_addr; 1085 assign m_ctrlport_radio0_req_data = radio0_m_ctrlport_req_data; 1086 assign m_ctrlport_radio0_req_byte_en = radio0_m_ctrlport_req_byte_en; 1087 assign m_ctrlport_radio0_req_has_time = radio0_m_ctrlport_req_has_time; 1088 assign m_ctrlport_radio0_req_time = radio0_m_ctrlport_req_time; 1089 assign radio0_m_ctrlport_resp_ack = m_ctrlport_radio0_resp_ack; 1090 assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status; 1091 assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data; 1092 1093 assign m_ctrlport_radio1_req_wr = radio1_m_ctrlport_req_wr; 1094 assign m_ctrlport_radio1_req_rd = radio1_m_ctrlport_req_rd; 1095 assign m_ctrlport_radio1_req_addr = radio1_m_ctrlport_req_addr; 1096 assign m_ctrlport_radio1_req_data = radio1_m_ctrlport_req_data; 1097 assign m_ctrlport_radio1_req_byte_en = radio1_m_ctrlport_req_byte_en; 1098 assign m_ctrlport_radio1_req_has_time = radio1_m_ctrlport_req_has_time; 1099 assign m_ctrlport_radio1_req_time = radio1_m_ctrlport_req_time; 1100 assign radio1_m_ctrlport_resp_ack = m_ctrlport_radio1_resp_ack; 1101 assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status; 1102 assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data; 1103 1104 assign radio0_radio_rx_data = radio_rx_data_radio0; 1105 assign radio0_radio_rx_stb = radio_rx_stb_radio0; 1106 assign radio_rx_running_radio0 = radio0_radio_rx_running; 1107 assign radio_tx_data_radio0 = radio0_radio_tx_data; 1108 assign radio0_radio_tx_stb = radio_tx_stb_radio0; 1109 assign radio_tx_running_radio0 = radio0_radio_tx_running; 1110 1111 assign radio1_radio_rx_data = radio_rx_data_radio1; 1112 assign radio1_radio_rx_stb = radio_rx_stb_radio1; 1113 assign radio_rx_running_radio1 = radio1_radio_rx_running; 1114 assign radio_tx_data_radio1 = radio1_radio_tx_data; 1115 assign radio1_radio_tx_stb = radio_tx_stb_radio1; 1116 assign radio_tx_running_radio1 = radio1_radio_tx_running; 1117 1118 assign fifo0_axi_rst = axi_rst; 1119 assign m_axi_awid = fifo0_m_axi_awid; 1120 assign m_axi_awaddr = fifo0_m_axi_awaddr; 1121 assign m_axi_awlen = fifo0_m_axi_awlen; 1122 assign m_axi_awsize = fifo0_m_axi_awsize; 1123 assign m_axi_awburst = fifo0_m_axi_awburst; 1124 assign m_axi_awlock = fifo0_m_axi_awlock; 1125 assign m_axi_awcache = fifo0_m_axi_awcache; 1126 assign m_axi_awprot = fifo0_m_axi_awprot; 1127 assign m_axi_awqos = fifo0_m_axi_awqos; 1128 assign m_axi_awregion = fifo0_m_axi_awregion; 1129 assign m_axi_awuser = fifo0_m_axi_awuser; 1130 assign m_axi_awvalid = fifo0_m_axi_awvalid; 1131 assign fifo0_m_axi_awready = m_axi_awready; 1132 assign m_axi_wdata = fifo0_m_axi_wdata; 1133 assign m_axi_wstrb = fifo0_m_axi_wstrb; 1134 assign m_axi_wlast = fifo0_m_axi_wlast; 1135 assign m_axi_wuser = fifo0_m_axi_wuser; 1136 assign m_axi_wvalid = fifo0_m_axi_wvalid; 1137 assign fifo0_m_axi_wready = m_axi_wready; 1138 assign fifo0_m_axi_bid = m_axi_bid; 1139 assign fifo0_m_axi_bresp = m_axi_bresp; 1140 assign fifo0_m_axi_buser = m_axi_buser; 1141 assign fifo0_m_axi_bvalid = m_axi_bvalid; 1142 assign m_axi_bready = fifo0_m_axi_bready; 1143 assign m_axi_arid = fifo0_m_axi_arid; 1144 assign m_axi_araddr = fifo0_m_axi_araddr; 1145 assign m_axi_arlen = fifo0_m_axi_arlen; 1146 assign m_axi_arsize = fifo0_m_axi_arsize; 1147 assign m_axi_arburst = fifo0_m_axi_arburst; 1148 assign m_axi_arlock = fifo0_m_axi_arlock; 1149 assign m_axi_arcache = fifo0_m_axi_arcache; 1150 assign m_axi_arprot = fifo0_m_axi_arprot; 1151 assign m_axi_arqos = fifo0_m_axi_arqos; 1152 assign m_axi_arregion = fifo0_m_axi_arregion; 1153 assign m_axi_aruser = fifo0_m_axi_aruser; 1154 assign m_axi_arvalid = fifo0_m_axi_arvalid; 1155 assign fifo0_m_axi_arready = m_axi_arready; 1156 assign fifo0_m_axi_rid = m_axi_rid; 1157 assign fifo0_m_axi_rdata = m_axi_rdata; 1158 assign fifo0_m_axi_rresp = m_axi_rresp; 1159 assign fifo0_m_axi_rlast = m_axi_rlast; 1160 assign fifo0_m_axi_ruser = m_axi_ruser; 1161 assign fifo0_m_axi_rvalid = m_axi_rvalid; 1162 assign m_axi_rready = fifo0_m_axi_rready; 1163 1164 // Broadcaster/Listener Connections: 1165 assign radio0_radio_time = radio_time; 1166 1167 assign radio1_radio_time = radio_time; 1168 1169endmodule 1170