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Searched refs:secstate (Results 1 – 25 of 26) sorted by relevance

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/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dm_helper.c434 bool secstate) in write_v7m_control_spsel_for_secstate() argument
438 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
439 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
443 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()
2692 bool secstate, bool priv, bool negpri) in arm_v7m_mmu_idx_all() argument
2704 if (secstate) { in arm_v7m_mmu_idx_all()
2714 bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); in arm_v7m_mmu_idx_for_secstate_and_priv()
2716 return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); in arm_v7m_mmu_idx_for_secstate_and_priv()
2720 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
2723 !(env->v7m.control[secstate] & 1); in arm_v7m_mmu_idx_for_secstate()
[all …]
H A Dinternals.h800 bool secstate, bool priv, bool negpri);
807 bool secstate, bool priv);
810 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
H A Dhelper.c8315 void *opaque, int state, int secstate, in add_cpreg_to_hashtable() argument
8325 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable()
8331 r2->secure = secstate; in add_cpreg_to_hashtable()
8357 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
12682 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dm_helper.c435 bool secstate) in write_v7m_control_spsel_for_secstate() argument
439 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
440 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
444 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()
2815 bool secstate, bool priv, bool negpri) in arm_v7m_mmu_idx_all() argument
2827 if (secstate) { in arm_v7m_mmu_idx_all()
2837 bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); in arm_v7m_mmu_idx_for_secstate_and_priv()
2839 return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); in arm_v7m_mmu_idx_for_secstate_and_priv()
2843 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
2846 !(env->v7m.control[secstate] & 1); in arm_v7m_mmu_idx_for_secstate()
[all …]
H A Dinternals.h564 bool secstate, bool priv, bool negpri);
571 bool secstate, bool priv);
574 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dm_helper.c443 bool secstate) in write_v7m_control_spsel_for_secstate() argument
447 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
448 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
452 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()
2867 bool secstate, bool priv, bool negpri) in arm_v7m_mmu_idx_all() argument
2879 if (secstate) { in arm_v7m_mmu_idx_all()
2889 bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); in arm_v7m_mmu_idx_for_secstate_and_priv()
2891 return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); in arm_v7m_mmu_idx_for_secstate_and_priv()
2895 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
2898 !(env->v7m.control[secstate] & 1); in arm_v7m_mmu_idx_for_secstate()
[all …]
H A Dinternals.h578 bool secstate, bool priv, bool negpri);
585 bool secstate, bool priv);
588 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
H A Dhelper.c8769 void *opaque, int state, int secstate, in add_cpreg_to_hashtable() argument
8779 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable()
8785 r2->secure = secstate; in add_cpreg_to_hashtable()
8811 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
13266 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dm_helper.c443 bool secstate) in write_v7m_control_spsel_for_secstate() argument
447 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
448 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
452 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()
2867 bool secstate, bool priv, bool negpri) in arm_v7m_mmu_idx_all() argument
2879 if (secstate) { in arm_v7m_mmu_idx_all()
2889 bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); in arm_v7m_mmu_idx_for_secstate_and_priv()
2891 return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); in arm_v7m_mmu_idx_for_secstate_and_priv()
2895 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
2898 !(env->v7m.control[secstate] & 1); in arm_v7m_mmu_idx_for_secstate()
[all …]
H A Dinternals.h586 bool secstate, bool priv, bool negpri);
593 bool secstate, bool priv);
596 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
H A Dhelper.c8507 void *opaque, int state, int secstate, in add_cpreg_to_hashtable() argument
8517 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable()
8523 r2->secure = secstate; in add_cpreg_to_hashtable()
8549 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
13004 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dm_helper.c432 bool secstate) in write_v7m_control_spsel_for_secstate() argument
436 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
437 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
441 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()
2687 bool secstate, bool priv, bool negpri) in arm_v7m_mmu_idx_all() argument
2699 if (secstate) { in arm_v7m_mmu_idx_all()
2707 bool secstate, bool priv) in arm_v7m_mmu_idx_for_secstate_and_priv() argument
2709 bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); in arm_v7m_mmu_idx_for_secstate_and_priv()
2711 return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); in arm_v7m_mmu_idx_for_secstate_and_priv()
2715 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
[all …]
H A Dcpu.h2955 bool secstate, bool priv, bool negpri);
2961 bool secstate, bool priv);
2964 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
H A Dhelper.c7084 void *opaque, int state, int secstate, in add_cpreg_to_hashtable() argument
7094 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable()
7100 r2->secure = secstate; in add_cpreg_to_hashtable()
7126 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
11128 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dm_helper.c432 bool secstate) in write_v7m_control_spsel_for_secstate() argument
436 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
437 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
441 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()
2689 bool secstate, bool priv, bool negpri) in arm_v7m_mmu_idx_all() argument
2701 if (secstate) { in arm_v7m_mmu_idx_all()
2709 bool secstate, bool priv) in arm_v7m_mmu_idx_for_secstate_and_priv() argument
2711 bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); in arm_v7m_mmu_idx_for_secstate_and_priv()
2713 return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); in arm_v7m_mmu_idx_for_secstate_and_priv()
2717 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
[all …]
H A Dinternals.h799 bool secstate, bool priv, bool negpri);
806 bool secstate, bool priv);
809 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
H A Dhelper.c8184 void *opaque, int state, int secstate, in add_cpreg_to_hashtable() argument
8194 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable()
8200 r2->secure = secstate; in add_cpreg_to_hashtable()
8226 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
12377 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dm_helper.c432 bool secstate) in write_v7m_control_spsel_for_secstate() argument
436 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
437 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
441 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()
2687 bool secstate, bool priv, bool negpri) in arm_v7m_mmu_idx_all() argument
2699 if (secstate) { in arm_v7m_mmu_idx_all()
2707 bool secstate, bool priv) in arm_v7m_mmu_idx_for_secstate_and_priv() argument
2709 bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); in arm_v7m_mmu_idx_for_secstate_and_priv()
2711 return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); in arm_v7m_mmu_idx_for_secstate_and_priv()
2715 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
[all …]
H A Dcpu.h2955 bool secstate, bool priv, bool negpri);
2961 bool secstate, bool priv);
2964 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
H A Dhelper.c7084 void *opaque, int state, int secstate, in add_cpreg_to_hashtable() argument
7094 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable()
7100 r2->secure = secstate; in add_cpreg_to_hashtable()
7126 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
11128 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dm_helper.c432 bool secstate) in write_v7m_control_spsel_for_secstate() argument
436 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
437 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
441 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()
2689 bool secstate, bool priv, bool negpri) in arm_v7m_mmu_idx_all() argument
2701 if (secstate) { in arm_v7m_mmu_idx_all()
2709 bool secstate, bool priv) in arm_v7m_mmu_idx_for_secstate_and_priv() argument
2711 bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); in arm_v7m_mmu_idx_for_secstate_and_priv()
2713 return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); in arm_v7m_mmu_idx_for_secstate_and_priv()
2717 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
[all …]
H A Dinternals.h799 bool secstate, bool priv, bool negpri);
806 bool secstate, bool priv);
809 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
H A Dhelper.c8183 void *opaque, int state, int secstate, in add_cpreg_to_hashtable() argument
8193 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable()
8199 r2->secure = secstate; in add_cpreg_to_hashtable()
8225 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
12376 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dcpu.h2680 bool secstate, in arm_v7m_mmu_idx_for_secstate_and_priv() argument
2689 if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { in arm_v7m_mmu_idx_for_secstate_and_priv()
2693 if (secstate) { in arm_v7m_mmu_idx_for_secstate_and_priv()
2702 bool secstate) in arm_v7m_mmu_idx_for_secstate() argument
2706 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); in arm_v7m_mmu_idx_for_secstate()
H A Dhelper.c5738 void *opaque, int state, int secstate, in add_cpreg_to_hashtable() argument
5748 int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; in add_cpreg_to_hashtable()
5754 r2->secure = secstate; in add_cpreg_to_hashtable()
5780 } else if ((secstate != r->secure) && !ns) { in add_cpreg_to_hashtable()
6595 bool secstate) in write_v7m_control_spsel_for_secstate() argument
6599 env->v7m.control[secstate] = in write_v7m_control_spsel_for_secstate()
6600 deposit32(env->v7m.control[secstate], in write_v7m_control_spsel_for_secstate()
6604 if (secstate == env->v7m.secure) { in write_v7m_control_spsel_for_secstate()

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