/dports/cad/yosys/yosys-yosys-0.12/passes/pmgen/ |
H A D | ice40_dsp.cc | 89 cell->setPort(ID::A, A); in create_ice40_dsp() 90 cell->setPort(ID::B, B); in create_ice40_dsp() 112 cell->setPort(ID(AHOLD), AHOLD); in create_ice40_dsp() 113 cell->setPort(ID(BHOLD), BHOLD); in create_ice40_dsp() 114 cell->setPort(ID(CHOLD), CDHOLD); in create_ice40_dsp() 115 cell->setPort(ID(DHOLD), CDHOLD); in create_ice40_dsp() 169 cell->setPort(ID::CI, State::Sx); in create_ice40_dsp() 184 cell->setPort(ID::CO, O[32]); in create_ice40_dsp() 193 cell->setPort(ID::O, O); in create_ice40_dsp() 222 cell->setPort(ID(ORSTTOP), ORST); in create_ice40_dsp() [all …]
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H A D | xilinx_dsp.cc | 179 cell->setPort(ID::C, C); in xilinx_simd_pack() 180 cell->setPort(ID::P, P); in xilinx_simd_pack() 243 cell->setPort(ID::C, C); in xilinx_simd_pack() 244 cell->setPort(ID::P, P); in xilinx_simd_pack() 413 cell->setPort(ID::A, A); in xilinx_dsp_pack() 428 cell->setPort(ID::B, B); in xilinx_dsp_pack() 434 cell->setPort(ID::D, D); in xilinx_dsp_pack() 481 cell->setPort(ID::P, P); in xilinx_dsp_pack() 598 cell->setPort(ID::A, A); in xilinx_dsp48a_pack() 611 cell->setPort(ID::B, B); in xilinx_dsp48a_pack() [all …]
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H A D | ice40_wrapcarry.cc | 43 cell->setPort(ID::A, st.carry->getPort(ID(I0))); in create_ice40_wrapcarry() 44 cell->setPort(ID::B, st.carry->getPort(ID(I1))); in create_ice40_wrapcarry() 46 cell->setPort(ID::CI, CI); in create_ice40_wrapcarry() 47 cell->setPort(ID::CO, st.carry->getPort(ID::CO)); in create_ice40_wrapcarry() 49 cell->setPort(ID(I0), st.lut->getPort(ID(I0))); in create_ice40_wrapcarry() 57 cell->setPort(ID(I3), I3); in create_ice40_wrapcarry() 58 cell->setPort(ID::O, st.lut->getPort(ID::O)); in create_ice40_wrapcarry() 120 carry->setPort(ID(I0), cell->getPort(ID::A)); in execute() 121 carry->setPort(ID(I1), cell->getPort(ID::B)); in execute() 122 carry->setPort(ID::CI, cell->getPort(ID::CI)); in execute() [all …]
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H A D | xilinx_srl.cc | 88 c->setPort(ID::C, first_cell->getPort(ID::C)); in run_fixed() 89 c->setPort(ID::D, first_cell->getPort(ID::D)); in run_fixed() 90 c->setPort(ID::Q, last_cell->getPort(ID::Q)); in run_fixed() 91 c->setPort(ID::L, GetSize(ud.longest_chain)-1); in run_fixed() 93 c->setPort(ID::E, State::S1); in run_fixed() 95 c->setPort(ID::E, first_cell->getPort(ID::E)); in run_fixed() 97 c->setPort(ID::E, first_cell->getPort(ID(CE))); in run_fixed() 166 c->setPort(ID::C, first_cell->getPort(ID::C)); in run_variable() 172 c->setPort(ID::Q, st.shiftx->getPort(ID::Y)); in run_variable() 173 c->setPort(ID::L, st.shiftx->getPort(ID::B)); in run_variable() [all …]
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H A D | xilinx_srl.pmg | 31 cell->setPort(\C, C); 32 cell->setPort(\D, D); 33 cell->setPort(\Q, Q); 34 cell->setPort(\CE, module->addWire(NEW_ID)); 36 cell->setPort(\R, module->addWire(NEW_ID)); 39 cell->setPort(\R, State::S0); 147 cell->setPort(\C, chain.back()->getPort(\C)); 148 cell->setPort(\D, module->addWire(NEW_ID)); 149 cell->setPort(\Q, chain.back()->getPort(\D)); 309 cell->setPort(\C, back->getPort(\C)); [all …]
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/dports/cad/yosys/yosys-yosys-0.12/passes/proc/ |
H A D | proc_dff.cc | 136 cell->setPort(ID::D, sig_d); in gen_dffsr_complex() 137 cell->setPort(ID::Q, sig_q); in gen_dffsr_complex() 138 cell->setPort(ID::CLK, clk); in gen_dffsr_complex() 158 cell->setPort(ID::D, sig_in); in gen_aldff() 159 cell->setPort(ID::Q, sig_out); in gen_aldff() 160 cell->setPort(ID::AD, sig_set); in gen_aldff() 161 cell->setPort(ID::CLK, clk); in gen_aldff() 162 cell->setPort(ID::ALOAD, set); in gen_aldff() 186 cell->setPort(ID::D, sig_in); in gen_dff() 187 cell->setPort(ID::Q, sig_out); in gen_dff() [all …]
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H A D | proc_memwr.cc | 52 cell->setPort(ID::ADDR, memwr.address); in proc_memwr() 53 cell->setPort(ID::DATA, memwr.data); in proc_memwr() 64 cell->setPort(ID::EN, enable); in proc_memwr() 66 cell->setPort(ID::CLK, State::Sx); in proc_memwr() 70 cell->setPort(ID::CLK, sr->signal); in proc_memwr() 74 cell->setPort(ID::CLK, sr->signal); in proc_memwr()
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/dports/cad/yosys/yosys-yosys-0.12/passes/techmap/ |
H A D | muxcover.cc | 520 cell->setPort(ID::A, mux.inputs[0]); in implement_best_cover() 521 cell->setPort(ID::B, mux.inputs[1]); in implement_best_cover() 523 cell->setPort(ID::Y, bit); in implement_best_cover() 530 cell->setPort(ID::A, mux.inputs[0]); in implement_best_cover() 531 cell->setPort(ID::B, mux.inputs[1]); in implement_best_cover() 532 cell->setPort(ID::C, mux.inputs[2]); in implement_best_cover() 533 cell->setPort(ID::D, mux.inputs[3]); in implement_best_cover() 536 cell->setPort(ID::Y, bit); in implement_best_cover() 543 cell->setPort(ID::A, mux.inputs[0]); in implement_best_cover() 554 cell->setPort(ID::Y, bit); in implement_best_cover() [all …]
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H A D | simplemap.cc | 40 gate->setPort(ID::A, sig_a[i]); in simplemap_not() 41 gate->setPort(ID::Y, sig_y[i]); in simplemap_not() 88 gate->setPort(ID::A, sig_a[i]); in simplemap_bitop() 152 gate->setPort(ID::A, sig_a); in simplemap_reduce() 153 gate->setPort(ID::Y, sig_t); in simplemap_reduce() 209 gate->setPort(ID::A, sig_a); in simplemap_lognot() 210 gate->setPort(ID::Y, sig_y); in simplemap_lognot() 238 gate->setPort(ID::A, sig_a); in simplemap_logbin() 239 gate->setPort(ID::B, sig_b); in simplemap_logbin() 240 gate->setPort(ID::Y, sig_y); in simplemap_logbin() [all …]
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H A D | maccmap.cc | 116 cell->setPort(ID::A, in1); in fulladd() 117 cell->setPort(ID::B, in2); in fulladd() 118 cell->setPort(ID::C, in3); in fulladd() 119 cell->setPort(ID::Y, w1); in fulladd() 120 cell->setPort(ID::X, w2); in fulladd() 241 c->setPort(ID::A, summands.front()); in synth() 242 c->setPort(ID::B, summands.back()); in synth() 243 c->setPort(ID::CI, State::S0); in synth() 244 c->setPort(ID::BI, State::S0); in synth() 245 c->setPort(ID::Y, module->addWire(NEW_ID, width)); in synth() [all …]
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/dports/cad/yosys/yosys-yosys-0.12/frontends/liberty/ |
H A D | liberty.cc | 59 cell->setPort(ID::A, A); in create_inv_cell() 67 cell->setPort(ID::A, A); in create_xor_cell() 68 cell->setPort(ID::B, B); in create_xor_cell() 76 cell->setPort(ID::A, A); in create_and_cell() 77 cell->setPort(ID::B, B); in create_and_cell() 85 cell->setPort(ID::A, A); in create_or_cell() 86 cell->setPort(ID::B, B); in create_or_cell() 263 cell->setPort(ID::A, iq_sig); in create_ff() 268 cell->setPort(ID::Q, iq_sig); in create_ff() 346 cell->setPort(ID::A, iq_sig); in create_latch() [all …]
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/dports/cad/yosys/yosys-yosys-0.12/passes/sat/ |
H A D | miter.cc | 131 gold_cell->setPort(gold_wire->name, w); in create_miter_equiv() 132 gate_cell->setPort(gold_wire->name, w); in create_miter_equiv() 172 or_gold_cell->setPort(ID::A, w_gold); in create_miter_equiv() 173 or_gold_cell->setPort(ID::B, gold_x); in create_miter_equiv() 182 or_gate_cell->setPort(ID::A, w_gate); in create_miter_equiv() 183 or_gate_cell->setPort(ID::B, gold_x); in create_miter_equiv() 192 eq_cell->setPort(ID::A, gold_masked); in create_miter_equiv() 193 eq_cell->setPort(ID::B, gate_masked); in create_miter_equiv() 205 eq_cell->setPort(ID::A, w_gold); in create_miter_equiv() 206 eq_cell->setPort(ID::B, w_gate); in create_miter_equiv() [all …]
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/dports/cad/yosys/yosys-yosys-0.12/techlibs/coolrunner2/ |
H A D | coolrunner2_fixup.cc | 39 xor_cell->setPort(ID(OUT), outwire); in makexorbuffer() 50 xor_cell->setPort(ID(OUT), outwire); in makexorbuffer() 62 xor_cell->setPort(ID(OUT), outwire); in makexorbuffer() 79 and_cell->setPort(ID(OUT), and_to_xor_wire); in makexorbuffer() 80 and_cell->setPort(ID(IN), inwire); in makexorbuffer() 81 and_cell->setPort(ID(IN_B), SigSpec()); in makexorbuffer() 88 xor_cell->setPort(ID(OUT), outwire); in makexorbuffer() 106 and_cell->setPort(ID(OUT), outwire); in makeptermbuffer() 107 and_cell->setPort(ID(IN), inwire); in makeptermbuffer() 108 and_cell->setPort(ID(IN_B), SigSpec()); in makeptermbuffer() [all …]
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H A D | coolrunner2_sop.cc | 145 and_cell->setPort(ID(OUT), and_out); in execute() 146 and_cell->setPort(ID(IN), and_in_true); in execute() 147 and_cell->setPort(ID(IN_B), and_in_comp); in execute() 157 xor_cell->setPort(ID(IN_PTC), *intermed_wires.begin()); in execute() 158 xor_cell->setPort(ID(OUT), sop_output); in execute() 167 std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin()); in execute() 190 std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin()); in execute() 208 or_cell->setPort(ID(IN), intermed_wires); in execute() 209 or_cell->setPort(ID(OUT), or_to_xor_wire); in execute() 216 xor_cell->setPort(ID(IN_ORTERM), or_to_xor_wire); in execute() [all …]
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/dports/cad/yosys/yosys-yosys-0.12/passes/fsm/ |
H A D | fsm_map.cc | 78 eq_cell->setPort(ID::A, eq_sig_a); in implement_pattern_cache() 79 eq_cell->setPort(ID::B, eq_sig_b); in implement_pattern_cache() 80 eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire)); in implement_pattern_cache() 106 or_cell->setPort(ID::A, or_sig); in implement_pattern_cache() 145 or_cell->setPort(ID::A, cases_vector); in implement_pattern_cache() 146 or_cell->setPort(ID::Y, output); in implement_pattern_cache() 216 eq_cell->setPort(ID::A, sig_a); in map_fsm() 217 eq_cell->setPort(ID::B, sig_b); in map_fsm() 289 mux_cell->setPort(ID::A, sig_a); in map_fsm() 290 mux_cell->setPort(ID::B, sig_b); in map_fsm() [all …]
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/dports/cad/yosys/yosys-yosys-0.12/kernel/ |
H A D | rtlil.cc | 2534 cell->setPort(ID::A, sig_a); in DEF_METHOD_2() 2535 cell->setPort(ID::B, sig_b); in DEF_METHOD_2() 2536 cell->setPort(ID::Y, sig_y); in DEF_METHOD_2() 2547 cell->setPort(ID::A, sig_a); in addSlice() 2548 cell->setPort(ID::Y, sig_y); in addSlice() 2558 cell->setPort(ID::A, sig_a); in addConcat() 3090 cell->setPort(ID::Y, sig); in Anyconst() 3100 cell->setPort(ID::Y, sig); in Anyseq() 3110 cell->setPort(ID::Y, sig); in Allconst() 3120 cell->setPort(ID::Y, sig); in Allseq() [all …]
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/dports/cad/yosys/yosys-yosys-0.12/passes/opt/ |
H A D | opt_lut_ins.cc | 228 cell->setPort(ID::A, new_inputs); in execute() 232 cell->setPort(ID::A, new_inputs[0]); in execute() 233 cell->setPort(ID::B, new_inputs[1]); in execute() 234 cell->setPort(ID::C, new_inputs[2]); in execute() 235 cell->setPort(ID::D, new_inputs[3]); in execute() 263 cell->setPort(ID(I0), new_inputs[0]); in execute() 265 cell->setPort(ID(I1), new_inputs[1]); in execute() 267 cell->setPort(ID(I2), new_inputs[2]); in execute() 269 cell->setPort(ID(I3), new_inputs[3]); in execute() 271 cell->setPort(ID(I4), new_inputs[4]); in execute() [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/catapult/third_party/pyserial/serial/urlhandler/ |
H A D | protocol_hwgrep.py | 20 def setPort(self, value): member in Serial 23 serial.Serial.setPort(self, self.fromURL(value)) 25 serial.Serial.setPort(self, value) 37 port = property(serial.Serial.getPort, setPort, doc="Port setting")
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/dports/devel/poco/poco-1.10.1-all/NetSSL_OpenSSL/src/ |
H A D | HTTPSClientSession.cpp | 38 setPort(HTTPS_PORT); in HTTPSClientSession() 46 setPort(HTTPS_PORT); in HTTPSClientSession() 55 setPort(HTTPS_PORT); in HTTPSClientSession() 64 setPort(port); in HTTPSClientSession() 88 setPort(port); in HTTPSClientSession() 98 setPort(port); in HTTPSClientSession()
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/dports/net/libksieve/libksieve-21.12.3/src/ksieveui/util/autotests/ |
H A D | findaccountinfojobtest.cpp | 88 info1.sieveUrl.setPort(port); in shouldAssignValue_data() 90 info1.sieveImapAccountSettings.setPort(imapPort); in shouldAssignValue_data() 128 info1.sieveUrl.setPort(port); in shouldAssignValue_data() 167 info1.sieveUrl.setPort(port); in shouldAssignValue_data() 207 info1.sieveUrl.setPort(port); in shouldAssignValue_data() 276 info1.sieveUrl.setPort(sievePort); in shouldAssignValue_data() 317 info1.sieveUrl.setPort(sievePort); in shouldAssignValue_data() 359 info1.sieveUrl.setPort(sievePort); in shouldAssignValue_data() 401 info1.sieveUrl.setPort(sievePort); in shouldAssignValue_data() 443 info1.sieveUrl.setPort(sievePort); in shouldAssignValue_data() [all …]
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/dports/cad/yosys/yosys-yosys-0.12/passes/tests/ |
H A D | test_cell.cc | 54 cell->setPort(ID::A, wire); in create_gold_module() 59 cell->setPort(ID::B, wire); in create_gold_module() 64 cell->setPort(ID::S, wire); in create_gold_module() 69 cell->setPort(ID::Y, wire); in create_gold_module() 79 cell->setPort(ID::A, wire); in create_gold_module() 84 cell->setPort(ID::B, wire); in create_gold_module() 89 cell->setPort(ID::C, wire); in create_gold_module() 94 cell->setPort(ID::X, wire); in create_gold_module() 99 cell->setPort(ID::Y, wire); in create_gold_module() 109 cell->setPort(ID::P, wire); in create_gold_module() [all …]
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/dports/cad/yosys/yosys-yosys-0.12/passes/memory/ |
H A D | memory_map.cc | 200 c->setPort(ID::CLK, refclock); in handle_memory() 208 c->setPort(ID::D, w_in); in handle_memory() 221 c->setPort(ID::Q, w_out); in handle_memory() 248 c->setPort(ID::Y, rd_signals[k]); in handle_memory() 249 c->setPort(ID::S, rd_addr.extract(abits-j-1, 1)); in handle_memory() 309 c->setPort(ID::A, w); in handle_memory() 310 c->setPort(ID::B, wr_bit); in handle_memory() 313 c->setPort(ID::Y, RTLIL::SigSpec(w)); in handle_memory() 318 c->setPort(ID::A, sig.extract(wr_offset, wr_width)); in handle_memory() 320 c->setPort(ID::S, RTLIL::SigSpec(w)); in handle_memory() [all …]
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/dports/devel/kiwix-lib/kiwix-lib-9.4.1/test/ |
H A D | kiwixserve.cpp | 8 kiwixServe.setPort(8484); in TEST() 10 EXPECT_EQ(kiwixServe.setPort(0), -1); in TEST() 11 EXPECT_EQ(kiwixServe.setPort(3456789), -1); in TEST()
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/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/ |
H A D | xilinx_dffopt.cc | 313 cell->setPort(ID::R, Const(0, 1)); in execute() 317 cell->setPort(ID::S, Const(0, 1)); in execute() 319 cell->setPort(ID(CE), Const(1, 1)); in execute() 349 cell->setPort(ID::D, lut_out); in execute() 350 lut_cell->setPort(ID::O, lut_out); in execute() 351 lut_cell->setPort(ID(I0), final_lut.second[0]); in execute() 353 lut_cell->setPort(ID(I1), final_lut.second[1]); in execute() 355 lut_cell->setPort(ID(I2), final_lut.second[2]); in execute() 357 lut_cell->setPort(ID(I3), final_lut.second[3]); in execute() 359 lut_cell->setPort(ID(I4), final_lut.second[4]); in execute() [all …]
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/dports/sysutils/bareos-traymonitor/bareos-Release-20.0.3/webui/vendor/zendframework/zend-view/src/Helper/ |
H A D | ServerUrl.php | 96 $this->setPort((int) $matches['port']); 127 $this->setPort(443); 130 $this->setPort($_SERVER['SERVER_PORT']); 210 $this->setPort($port); 291 public function setPort($port) function in Zend\\View\\Helper\\ServerUrl
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