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Searched refs:t_clr (Results 1 – 8 of 8) sorted by relevance

/dports/cad/gplcver/gplcver-2.12a.src/tests_and_examples/examples.acc/
H A Dnc_fdsp.v4 reg t_clk, t_clk0, t_clk1, t_clk2, t_d, t_clr, t_set; register
8 fd3noqn i3(t_q, t_clk, t_clk1, t_d, t_clr, t_set);
13 t_q, t_clk, t_d, t_clr, t_set);
18 #1000 t_clr = 0;
22 #1000 t_clr = 1'bx;
24 #1000 $display("testing normal logic"); t_clr = 1; t_set = 1; t_d = 0;
H A Dpchg_fdsp.v4 reg t_clk, t_clk0, t_clk1, t_clk2, t_d, t_clr, t_set; register
8 fd3noqn i3(t_q, t_clk, t_clk1, t_d, t_clr, t_set);
13 t_q, t_clk, t_d, t_clr, t_set);
18 #1000 t_clr = 0;
22 #1000 t_clr = 1'bx;
24 #1000 $display("testing normal logic"); t_clr = 1; t_set = 1; t_d = 0;
H A Daccxldrvtst.v4 reg t_clk, t_clk0, t_clk1, t_clk2, t_d, t_clr, t_set; register
8 fd3noqn i3(t_q, t_clk, t_clk1, t_d, t_clr, t_set);
14 t_q, t_clk, t_d, t_clr, t_set);
H A Dpchg_fdsp.plg18 Adding vcl for test.t_clr type accReg (fulltype accReg)
90 --> now 3000 (chg time 3000): test.t_clr=sr-scalar=0(0)
121 --> now 7000 (chg time 7000): test.t_clr=sr-scalar=2(x)
131 --> now 8000 (chg time 8000): test.t_clr=sr-scalar=1(1)
/dports/cad/gplcver/gplcver-2.12a.src/tests_and_examples/examples.vpi/
H A Dfdspec01.v4 reg t_clk, t_clk0, t_clk1, t_clk2, t_d, t_clr, t_set; register
8 fd3noqn i3(t_q, t_clk, t_clk1, t_d, t_clr, t_set);
13 t_q, t_clk, t_d, t_clr, t_set);
17 #1000 t_clr = 0;
21 #1000 t_clr = 1'bx;
23 #1000 $display("testing normal logic"); t_clr = 1; t_set = 1; t_d = 0;
H A Dvdrvld1.plg43 ... printing drivers and loads for test.t_clr:
/dports/mail/exmh2/exmh-2.9.0/lib/
H A Dapp-defaults997 *Sedit.Menubar.pgp.m.sign.t_clr: radio
1223 *WhatNow.more.m.encrypt.sign.t_clr: radio
/dports/comms/xastir/Xastir-Release-2.1.8/src/
H A Ddb.c4325 time_t t_clr, t_old, now; in display_file() local
4344 t_clr = now - sec_clear; in display_file()
4433 if (temp_sec_heard > t_clr) in display_file()