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Searched refs:target_write_u32 (Results 1 – 25 of 77) sorted by relevance

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/dports/devel/openocd/openocd-0.11.0/src/flash/nand/
H A Dlpc3180.c691 target_write_u32(target, in lpc3180_write_page()
701 target_write_u32(target, in lpc3180_write_page()
706 target_write_u32(target, in lpc3180_write_page()
733 target_write_u32(target, in lpc3180_write_page()
771 target_write_u32(target, in lpc3180_write_page()
1015 target_write_u32(target, in lpc3180_read_page()
1032 target_write_u32(target, in lpc3180_read_page()
1046 target_write_u32(target, in lpc3180_read_page()
1057 target_write_u32(target, in lpc3180_read_page()
1075 target_write_u32(target, in lpc3180_read_page()
[all …]
H A Dlpc32xx.c291 retval = target_write_u32(target, 0x200b8034, in lpc32xx_init()
334 retval = target_write_u32(target, 0x20020014, in lpc32xx_init()
374 retval = target_write_u32(target, 0x2002002c, in lpc32xx_init()
622 retval = target_write_u32(target, 0x200b8004, in lpc32xx_write_page_mlc()
630 retval = target_write_u32(target, 0x200b8004, in lpc32xx_write_page_mlc()
656 retval = target_write_u32(target, 0x200b8004, in lpc32xx_write_page_mlc()
926 retval = target_write_u32(target, 0x31000110, in lpc32xx_start_slc_dma()
1190 retval = target_write_u32(target, 0x31000110, in lpc32xx_write_page_slc()
1329 retval = target_write_u32(target, 0x200b8004, in lpc32xx_read_page_mlc()
1364 retval = target_write_u32(target, 0x200b8004, in lpc32xx_read_page_mlc()
[all …]
H A Dnuc910.c70 target_write_u32(target, NUC910_SMADDR, ((address & 0xff) | NUC910_SMADDR_EOA)); in nuc910_nand_address()
207 target_write_u32(target, NUC910_FMICSR, NUC910_FMICSR_SM_EN); in nuc910_nand_init()
208 target_write_u32(target, NUC910_SMCSR, 0x010000a8); /* 2048 page size */ in nuc910_nand_init()
209 target_write_u32(target, NUC910_SMTCR, 0x00010204); in nuc910_nand_init()
210 target_write_u32(target, NUC910_SMIER, 0x00000000); in nuc910_nand_init()
/dports/devel/openocd/openocd-0.11.0/src/flash/nor/
H A Dtms470.c425 target_write_u32(target, 0xFFE89C00, 0x00); in tms470_try_flash_keys()
536 target_write_u32(target, 0xFFE8A07C, 50); in tms470_flash_initialize_internal_state_machine()
585 target_write_u32(target, 0xFFE8A05C, k); in tms470_flash_initialize_internal_state_machine()
592 target_write_u32(target, 0xFFE8A034, k); in tms470_flash_initialize_internal_state_machine()
594 target_write_u32(target, 0xFFE8A040, k); in tms470_flash_initialize_internal_state_machine()
596 target_write_u32(target, 0xFFE8A024, k); in tms470_flash_initialize_internal_state_machine()
603 target_write_u32(target, 0xFFE8A060, k); in tms470_flash_initialize_internal_state_machine()
610 target_write_u32(target, 0xFFE8A020, k); in tms470_flash_initialize_internal_state_machine()
617 target_write_u32(target, 0xFFE8A038, k); in tms470_flash_initialize_internal_state_machine()
701 target_write_u32(target, 0xFFE89C00, 0); in tms470_erase_sector()
[all …]
H A Dmdr.c102 retval = target_write_u32(target, FLASH_ADR, i << 2); in mdr_mass_erase()
107 retval = target_write_u32(target, FLASH_CMD, flash_cmd); in mdr_mass_erase()
111 retval = target_write_u32(target, FLASH_CMD, flash_cmd); in mdr_mass_erase()
115 retval = target_write_u32(target, FLASH_CMD, flash_cmd); in mdr_mass_erase()
154 retval = target_write_u32(target, FLASH_KEY, KEY); in mdr_erase()
166 retval = target_write_u32(target, FLASH_CMD, flash_cmd); in mdr_erase()
209 retval2 = target_write_u32(target, FLASH_KEY, 0); in mdr_erase()
359 retval = target_write_u32(target, FLASH_KEY, KEY); in mdr_write()
456 retval2 = target_write_u32(target, FLASH_KEY, 0); in mdr_write()
515 retval = target_write_u32(target, FLASH_KEY, KEY); in mdr_read()
[all …]
H A Dem357.c205 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2); in em357_erase_options()
247 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2); in em357_write_options()
360 target_write_u32(target, EM357_FPEC_CLK, 0x00000001); in em357_erase()
366 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2); in em357_erase()
374 retval = target_write_u32(target, EM357_FLASH_AR, in em357_erase()
555 target_write_u32(target, EM357_FLASH_SR, FLASH_PGERR); in em357_write_block()
605 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1); in em357_write()
608 retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2); in em357_write()
612 target_write_u32(target, EM357_FPEC_CLK, 0x00000001); in em357_write()
840 target_write_u32(target, EM357_FPEC_CLK, 0x00000001); in em357_mass_erase()
[all …]
H A Dambiqmicro.c382 retval = target_write_u32(target, 0x400201a0, 0x0); in ambiqmicro_mass_erase()
404 retval = target_write_u32(target, 0x10000008, 0xfffffffe); in ambiqmicro_mass_erase()
423 retval = target_write_u32(target, 0x400201a0, 0x1); in ambiqmicro_mass_erase()
464 retval = target_write_u32(target, 0x400201a0, 0x0); in ambiqmicro_erase()
498 retval = target_write_u32(target, 0x10000010, first); in ambiqmicro_erase()
522 retval = target_write_u32(target, 0x400201a0, 0x1); in ambiqmicro_erase()
587 retval = target_write_u32(target, 0x10000000, address); in ambiqmicro_write_block()
635 retval = target_write_u32(target, 0x400201a0, 0x0); in ambiqmicro_write_block()
724 retval = target_write_u32(target, 0x400201a0, 0x0); in ambiqmicro_otp_program()
734 retval = target_write_u32(target, 0x10000000, offset); in ambiqmicro_otp_program()
[all …]
H A Dstr7x.c352 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0); in str7x_erase()
407 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0); in str7x_protect()
417 err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd); in str7x_protect()
599 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0); in str7x_write()
623 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd); in str7x_write()
626 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address); in str7x_write()
640 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd); in str7x_write()
663 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd); in str7x_write()
666 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address); in str7x_write()
678 target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd); in str7x_write()
[all …]
H A Dswm050.c53 retval = target_write_u32(target, SWM050_FLASH_REG1, 0x4); in swm050_erase()
60 retval = target_write_u32(target, curr_addr, SWM050_FLASH_KEY); in swm050_erase()
67 retval = target_write_u32(target, SWM050_FLASH_REG1, 0x0); in swm050_erase()
86 retval = target_write_u32(target, SWM050_FLASH_REG1, 0x1); in swm050_write()
95 retval = target_write_u32(target, SWM050_FLASH_REG1, 0x0); in swm050_write()
118 retval = target_write_u32(target, SWM050_FLASH_REG1, 0x6); in swm050_mass_erase()
121 retval = target_write_u32(target, SWM050_FLASH_REG2, 0x1); in swm050_mass_erase()
124 retval = target_write_u32(target, 0x0, SWM050_FLASH_KEY); in swm050_mass_erase()
131 retval = target_write_u32(target, SWM050_FLASH_REG1, 0x0); in swm050_mass_erase()
H A Dlpc2900.c407 target_write_u32(target, FCTR, in lpc2900_write_index_page()
412 target_write_u32(target, FCTR, in lpc2900_write_index_page()
429 target_write_u32(target, FPTR, in lpc2900_write_index_page()
434 target_write_u32(target, FCTR, in lpc2900_write_index_page()
998 target_write_u32(target, FPTR, in lpc2900_erase()
1010 target_write_u32(target, FCTR, in lpc2900_erase()
1018 target_write_u32(target, FCTR, in lpc2900_erase()
1021 target_write_u32(target, FCTR, in lpc2900_erase()
1126 target_write_u32(target, FCTR, in lpc2900_write()
1307 target_write_u32(target, FCTR, in lpc2900_write()
[all …]
H A Dmax32xxx.c182 target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); in max32xxx_flash_op_pre()
204 target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); in max32xxx_flash_op_post()
282 target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); in max32xxx_erase()
286 target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); in max32xxx_erase()
304 target_write_u32(target, info->flc_base + FLSH_INT, 0); in max32xxx_erase()
484 target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); in max32xxx_write()
510 target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); in max32xxx_write()
541 target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); in max32xxx_write()
733 target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); in max32xxx_mass_erase()
737 target_write_u32(target, info->flc_base + FLSH_CN, flsh_cn); in max32xxx_mass_erase()
[all …]
H A Dstellaris.c872 target_write_u32(target, FLASH_CIM, 0); in stellaris_erase()
894 target_write_u32(target, FLASH_CRIS, 0); in stellaris_erase()
943 target_write_u32(target, FLASH_CIM, 0); in stellaris_protect()
975 target_write_u32(target, fmppe_addr, fmppe); in stellaris_protect()
991 target_write_u32(target, FLASH_CRIS, 0); in stellaris_protect()
1157 target_write_u32(target, FLASH_CIM, 0); in stellaris_write()
1191 target_write_u32(target, FLASH_FMA, address); in stellaris_write()
1215 target_write_u32(target, FLASH_FMA, address); in stellaris_write()
1291 target_write_u32(target, FLASH_CIM, 0); in stellaris_mass_erase()
1298 target_write_u32(target, FLASH_FMA, 0); in stellaris_mass_erase()
[all …]
H A Dstm32f1x.c205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), in stm32x_wait_status_busy()
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1); in stm32x_erase_options()
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2); in stm32x_erase_options()
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1); in stm32x_erase_options()
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2); in stm32x_erase_options()
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1); in stm32x_write_options()
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2); in stm32x_write_options()
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1); in stm32x_write_options()
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2); in stm32x_write_options()
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK); in stm32x_write_options()
[all …]
H A Dlpc288x.c204 target_write_u32(bank->target, F_CTRL, FC_CS | FC_WEN); in lpc288x_set_flash_clk()
205 target_write_u32(bank->target, F_CLK_TIME, clk_time); in lpc288x_set_flash_clk()
217 target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 9500); in lpc288x_load_timer()
219 target_write_u32(target, F_PROG_TIME, FPT_ENABLE | 75); in lpc288x_load_timer()
259 target_write_u32(target, bank->sectors[sector].offset, 0x00); in lpc288x_erase()
261 target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_CS); in lpc288x_erase()
337 target_write_u32(target, F_CTRL, FC_CS | FC_SET_DATA | FC_WEN | FC_FUNC); in lpc288x_write()
339 target_write_u32(target, F_CTRL, FC_CS | FC_WEN | FC_FUNC); in lpc288x_write()
353 target_write_u32(target, F_CTRL, FC_PROG_REQ | FC_PROTECT | FC_FUNC | in lpc288x_write()
407 target_write_u32(target, bank->sectors[lockregion].offset, value); in lpc288x_protect()
[all …]
H A Drenesas_rpchf.c198 return target_write_u32(target, reg, val); in clrsetbits_u32()
229 ret = target_write_u32(target, rpc_base + RPC_DRCR, in rpc_hf_mode()
235 ret = target_write_u32(target, rpc_base + RPC_DRCMR, in rpc_hf_mode()
239 ret = target_write_u32(target, rpc_base + RPC_DRENR, in rpc_hf_mode()
247 ret = target_write_u32(target, rpc_base + RPC_DRDMCR, in rpc_hf_mode()
252 ret = target_write_u32(target, rpc_base + RPC_DRDRENR, in rpc_hf_mode()
303 ret = target_write_u32(target, rpc_base + RPC_SMCMR, in rpc_hf_xfer()
308 ret = target_write_u32(target, rpc_base + RPC_SMADR, in rpc_hf_xfer()
317 ret = target_write_u32(target, rpc_base + RPC_SMDRENR, in rpc_hf_xfer()
341 ret = target_write_u32(target, rpc_base + RPC_SMCR, in rpc_hf_xfer()
[all …]
H A Dniietcm4.c180 retval = target_write_u32(target, FCIC, flash_cmd); in niietcm4_opstatus_check()
217 retval = target_write_u32(target, UFCIC, uflash_cmd); in niietcm4_uopstatus_check()
246 retval = target_write_u32(target, UFMA, i); in niietcm4_dump_uflash_page()
249 retval = target_write_u32(target, UFMC, uflash_cmd); in niietcm4_dump_uflash_page()
282 retval = target_write_u32(target, UFMA, i); in niietcm4_load_uflash_page()
285 retval = target_write_u32(target, UFMD, dump[i]); in niietcm4_load_uflash_page()
316 retval = target_write_u32(target, UFMD, 0xFF); in niietcm4_uflash_page_erase()
319 retval = target_write_u32(target, UFMC, uflash_cmd); in niietcm4_uflash_page_erase()
419 retval = target_write_u32(target, UFMC, uflash_cmd); in COMMAND_HANDLER()
1155 retval = target_write_u32(target, FMC, flash_cmd); in niietcm4_mass_erase()
[all …]
H A Desirisc_flash.c142 target_write_u32(target, esirisc_info->cfg + UNLOCK1, 0x7123); in esirisc_flash_unlock()
143 target_write_u32(target, esirisc_info->cfg + UNLOCK2, 0x812a); in esirisc_flash_unlock()
144 target_write_u32(target, esirisc_info->cfg + UNLOCK1, 0xbee1); in esirisc_flash_unlock()
163 target_write_u32(target, esirisc_info->cfg + CONTROL, control); in esirisc_flash_disable_protect()
182 target_write_u32(target, esirisc_info->cfg + CONTROL, control); in esirisc_flash_enable_protect()
295 target_write_u32(target, esirisc_info->cfg + ADDRESS, 0); in esirisc_flash_mass_erase()
341 target_write_u32(target, esirisc_info->cfg + PB_INDEX, 0); in esirisc_flash_fill_pb()
378 target_write_u32(target, esirisc_info->cfg + ADDRESS, offset); in esirisc_flash_write()
435 target_write_u32(target, esirisc_info->cfg + TIMING0, value); in esirisc_flash_init()
440 target_write_u32(target, esirisc_info->cfg + TIMING1, value); in esirisc_flash_init()
[all …]
H A Dstmqspi.c281 retval = target_write_u32(target, io_base + SPI_CR, in set_mm_mode()
305 retval = target_write_u32(target, io_base + QSPI_CR, in set_mm_mode()
324 retval = target_write_u32(target, io_base + SPI_CR, in read_status_reg()
336 retval = target_write_u32(target, io_base + SPI_DLR, in read_status_reg()
419 retval = target_write_u32(target, io_base + SPI_CR, in qspi_write_enable()
826 retval = target_write_u32(target, io_base + SPI_CR, in COMMAND_HANDLER()
1085 retval = target_write_u32(target, io_base + SPI_CR, in stmqspi_blank_check()
1593 retval = target_write_u32(target, io_base + SPI_CR, in stmqspi_read()
1656 retval = target_write_u32(target, io_base + SPI_CR, in stmqspi_write()
1707 retval = target_write_u32(target, io_base + SPI_CR, in stmqspi_verify()
[all …]
H A Dpsoc6.c150 hr = target_write_u32(target, 0xE000ED08, 0x00000000); in sromalgo_prepare()
167 hr = target_write_u32(target, g_stack_area->address, 0xFEE7FEE7); in sromalgo_prepare()
341 hr = target_write_u32(target, MEM_IPC_DATA(IPC_ID), working_area); in call_sromapi()
343 hr = target_write_u32(target, MEM_IPC_DATA(IPC_ID), req_and_params); in call_sromapi()
353 hr = target_write_u32(target, MEM_IPC_NOTIFY(IPC_ID), 1); in call_sromapi()
663 hr = target_write_u32(target, wa->address + 0x04, addr); in psoc6_erase_sector()
688 int hr = target_write_u32(target, wa->address, SROMAPI_ERASEROW_REQ); in psoc6_erase_row()
692 hr = target_write_u32(target, wa->address + 0x04, addr); in psoc6_erase_row()
795 hr = target_write_u32(target, wa->address, sromapi_req); in psoc6_program_row()
799 hr = target_write_u32(target, in psoc6_program_row()
[all …]
H A Dfm3.c267 retval = target_write_u32(target, 0x40011C00, 0x1ACCE551); in fm3_erase()
271 retval = target_write_u32(target, 0x40011C00, 0xE5331AAE); in fm3_erase()
275 retval = target_write_u32(target, 0x40011008, 0x00000000); in fm3_erase()
280 retval = target_write_u32(target, 0x40000000, 0x0001); in fm3_erase()
340 retval = target_write_u32(target, 0x40000000, 0x0002); in fm3_erase()
518 retval = target_write_u32(target, 0x40011C00, 0x1ACCE551); in fm3_write_block()
522 retval = target_write_u32(target, 0x40011C00, 0xE5331AAE); in fm3_write_block()
526 retval = target_write_u32(target, 0x40011008, 0x00000000); in fm3_write_block()
876 retval = target_write_u32(target, 0x40011C00, 0x1ACCE551); in fm3_chip_erase()
889 retval = target_write_u32(target, 0x40000000, 0x0001); in fm3_chip_erase()
[all …]
H A Daducm360.c117 target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEKEY, 0x0000F456); in aducm360_mass_erase()
118 target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEKEY, 0x0000F123); in aducm360_mass_erase()
120 target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEECMD, 0x00000003); in aducm360_mass_erase()
146 target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEKEY, 0x0000F456); in aducm360_page_erase()
147 target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEKEY, 0x0000F123); in aducm360_page_erase()
149 target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEADR0L, padd & 0xFFFF); in aducm360_page_erase()
150 target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEEADR0H, (padd>>16) & 0xFFFF); in aducm360_page_erase()
152 target_write_u32(target, ADUCM360_FLASH_BASE+ADUCM360_FLASH_FEECMD, 0x00000001); in aducm360_page_erase()
471 target_write_u32(target, a, d); in aducm360_write_modified()
523 target_write_u32(target, ADUCM360_FLASH_BASE + ADUCM360_FLASH_FEECON0, value); in aducm360_set_write_enable()
H A Dsim3x.c190 ret = target_write_u32(target, WDTIMER0_CONTROL_SET, in sim3x_init()
196 ret = target_write_u32(target, VMON0_CONTROL_SET, in sim3x_init()
202 ret = target_write_u32(target, RSTSRC0_RESETEN_SET, in sim3x_init()
208 ret = target_write_u32(target, CLKCTRL0_APBCLKG0_SET, in sim3x_init()
214 ret = target_write_u32(target, FLASHCTRL0_CONFIG_CLR, in sim3x_init()
242 ret = target_write_u32(target, FLASHCTRL0_CONFIG_SET, in sim3x_erase_page()
249 ret = target_write_u32(target, FLASHCTRL0_WRADDR, addr); in sim3x_erase_page()
254 ret = target_write_u32(target, FLASHCTRL0_KEY, in sim3x_erase_page()
260 ret = target_write_u32(target, FLASHCTRL0_KEY, in sim3x_erase_page()
266 ret = target_write_u32(target, FLASHCTRL0_WRDATA, 0); in sim3x_erase_page()
[all …]
H A Dstm32lx.c980 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, in stm32lx_unlock_program_memory()
985 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PEKEYR, in stm32lx_unlock_program_memory()
1001 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR, in stm32lx_unlock_program_memory()
1005 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PRGKEYR, in stm32lx_unlock_program_memory()
1044 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, in stm32lx_enable_write_half_page()
1055 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, in stm32lx_enable_write_half_page()
1076 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, in stm32lx_lock_program_memory()
1087 retval = target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR, in stm32lx_lock_program_memory()
1115 retval = target_write_u32(target, in stm32lx_erase_sector()
1126 retval = target_write_u32(target, addr, 0x0); in stm32lx_erase_sector()
[all …]
H A Dnumicro.c1153 retval = target_write_u32(target, NUMICRO_SYS_WRPROT, REG_KEY1); in numicro_reg_unlock()
1156 retval = target_write_u32(target, NUMICRO_SYS_WRPROT, REG_KEY2); in numicro_reg_unlock()
1159 retval = target_write_u32(target, NUMICRO_SYS_WRPROT, REG_KEY3); in numicro_reg_unlock()
1197 retval = target_write_u32(target, NUMICRO_SYSCLK_AHBCLK, reg_stat); in numicro_init_isp()
1207 retval = target_write_u32(target, NUMICRO_FLASH_ISPCON, reg_stat); in numicro_init_isp()
1212 retval = target_write_u32(target, NUMICRO_FLASH_CHEAT, 1); in numicro_init_isp()
1224 retval = target_write_u32(target, NUMICRO_FLASH_ISPCMD, cmd); in numicro_fmc_cmd()
1228 retval = target_write_u32(target, NUMICRO_FLASH_ISPDAT, wdata); in numicro_fmc_cmd()
1232 retval = target_write_u32(target, NUMICRO_FLASH_ISPADR, addr); in numicro_fmc_cmd()
1236 retval = target_write_u32(target, NUMICRO_FLASH_ISPTRG, ISPTRG_ISPGO); in numicro_fmc_cmd()
[all …]
/dports/devel/openocd/openocd-0.11.0/src/target/
H A Darmv7m_trace.c122 retval = target_write_u32(target, TPIU_CSPSR, 1 << trace_config->port_size); in armv7m_trace_tpiu_config()
126 retval = target_write_u32(target, TPIU_ACPR, prescaler - 1); in armv7m_trace_tpiu_config()
130 retval = target_write_u32(target, TPIU_SPPR, trace_config->pin_protocol); in armv7m_trace_tpiu_config()
142 retval = target_write_u32(target, TPIU_FFCR, ffcr); in armv7m_trace_tpiu_config()
161 retval = target_write_u32(target, ITM_LAR, ITM_LAR_KEY); in armv7m_trace_itm_config()
166 retval = target_write_u32(target, ITM_TCR, (1 << 0) | (1 << 3) | in armv7m_trace_itm_config()
176 retval = target_write_u32(target, ITM_TER0 + i * 4, in armv7m_trace_itm_config()

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