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/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_sys_rand.v10 reg [31:0] thisrand; register
22 thisrand = $random;
24 $write("Random = %x\n", thisrand);
26 if (thisrand == lastrand) same=same+1;
27 lastrand = thisrand;