1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2008 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t; 8 9 reg [31:0] lastrand; 10 reg [31:0] thisrand; 11 12 integer same = 0; 13 integer i; 14 15`define TRIES 20 16 17 initial begin 18 // There's a 1^32 chance of the numbers being the same twice, 19 // so we'll allow one failure 20 lastrand = $random; 21 for (i=0; i<`TRIES; i=i+1) begin 22 thisrand = $random; 23`ifdef TEST_VERBOSE 24 $write("Random = %x\n", thisrand); 25`endif 26 if (thisrand == lastrand) same=same+1; 27 lastrand = thisrand; 28 end 29 if (same > 1) begin 30 $write("%%Error: Too many similar numbers: %d\n", same); 31 $stop; 32 end 33 $write("*-* All Finished *-*\n"); 34 $finish; 35 end 36 37endmodule 38