| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/compiler/ |
| H A D | brw_vec4.h | 154 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
165 vec4_instruction *inst, int arg);
167 vec4_instruction *emit(vec4_instruction *inst);
169 vec4_instruction *emit(enum opcode opcode);
171 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
173 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
179 vec4_instruction *emit_before(bblock_t *block,
180 vec4_instruction *inst,
181 vec4_instruction *new_inst);
209 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
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| /dports/lang/clover/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_vec4.h | 157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
212 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
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| H A D | brw_ir_vec4.h | 271 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
273 vec4_instruction(enum opcode opcode,
371 inline vec4_instruction *
373 vec4_instruction *inst) in set_predicate_inv()
383 inline vec4_instruction *
393 inline vec4_instruction *
404 inline vec4_instruction *
405 set_saturate(bool saturate, vec4_instruction *inst) in set_saturate()
418 regs_written(const vec4_instruction *inst) in regs_written()
441 get_exec_type(const vec4_instruction *inst) in get_exec_type()
[all …]
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| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_vec4.h | 157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
212 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
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| H A D | brw_ir_vec4.h | 271 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
273 vec4_instruction(enum opcode opcode,
371 inline vec4_instruction *
373 vec4_instruction *inst) in set_predicate_inv()
383 inline vec4_instruction *
393 inline vec4_instruction *
404 inline vec4_instruction *
405 set_saturate(bool saturate, vec4_instruction *inst) in set_saturate()
418 regs_written(const vec4_instruction *inst) in regs_written()
441 get_exec_type(const vec4_instruction *inst) in get_exec_type()
[all …]
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| /dports/graphics/libosmesa/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_vec4.h | 157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
212 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
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| H A D | brw_ir_vec4.h | 271 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
273 vec4_instruction(enum opcode opcode,
371 inline vec4_instruction *
373 vec4_instruction *inst) in set_predicate_inv()
383 inline vec4_instruction *
393 inline vec4_instruction *
404 inline vec4_instruction *
405 set_saturate(bool saturate, vec4_instruction *inst) in set_saturate()
418 regs_written(const vec4_instruction *inst) in regs_written()
441 get_exec_type(const vec4_instruction *inst) in get_exec_type()
[all …]
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| /dports/graphics/mesa-libs/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_vec4.h | 157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
212 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
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| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_vec4.h | 157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
212 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
|
| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_vec4.h | 157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
212 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
|
| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_vec4.h | 157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
212 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
|
| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_vec4.h | 157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
212 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
|
| /dports/graphics/mesa-dri/mesa-21.3.6/src/intel/compiler/ |
| H A D | brw_vec4.h | 157 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
168 vec4_instruction *inst, int arg);
170 vec4_instruction *emit(vec4_instruction *inst);
172 vec4_instruction *emit(enum opcode opcode);
174 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
176 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
182 vec4_instruction *emit_before(bblock_t *block,
183 vec4_instruction *inst,
184 vec4_instruction *new_inst);
212 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
|
| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/compiler/ |
| H A D | brw_vec4.h | 154 bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
165 vec4_instruction *inst, int arg);
167 vec4_instruction *emit(vec4_instruction *inst);
169 vec4_instruction *emit(enum opcode opcode);
171 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
173 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
179 vec4_instruction *emit_before(bblock_t *block,
180 vec4_instruction *inst,
181 vec4_instruction *new_inst);
209 vec4_instruction *IF(src_reg src0, src_reg src1,
[all …]
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| H A D | brw_vec4_visitor.cpp | 65 vec4_instruction *
76 vec4_instruction *
88 vec4_instruction *
96 vec4_instruction *
103 vec4_instruction *
109 vec4_instruction *
115 vec4_instruction *
193 vec4_instruction * in ALU1()
205 vec4_instruction *
228 vec4_instruction *
[all …]
|