| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/ |
| H A D | fifo_4kx16_dc.v | 46 wrfull,
58 output wrfull; port
68 wire wrfull = sub_wire2; net
81 .wrfull (sub_wire2),
|
| H A D | fifo_4k_18.v | 49 wrfull,
61 output wrfull; port
71 wire wrfull = sub_wire2; net
84 .wrfull (sub_wire2),
|
| H A D | fifo_2k_bb.v | 41 wrfull,
53 output wrfull; port
|
| H A D | fifo_4k_bb.v | 41 wrfull,
53 output wrfull; port
|
| H A D | fifo_4kx16_dc_bb.v | 41 wrfull,
53 output wrfull; port
|
| H A D | fifo_4kx16_dc_inst.v | 11 .wrfull ( wrfull_sig ),
|
| H A D | fifo_4kx16_dc.bsf | 71 (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8)))
72 (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))
|
| H A D | fifo_4kx16_dc.inc | 30 wrfull,
|
| H A D | fifo_4kx16_dc.cmp | 28 wrfull : OUT STD_LOGIC ;
|
| H A D | fifo_2k.v | 3023 wrfull,
3035 output wrfull; port
3210 wrfull = int_wrfull,
3229 wrfull,
3241 output wrfull; port
3251 wire wrfull = sub_wire2; net
3264 .wrfull (sub_wire2),
|
| H A D | fifo_4k.v | 3175 wrfull,
3187 output wrfull; port
3362 wrfull = int_wrfull,
3381 wrfull,
3393 output wrfull; port
3403 wire wrfull = sub_wire2; net
3416 .wrfull (sub_wire2),
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/models/ |
| H A D | fifo_1c_2k.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
20 output wrfull; port
76 assign wrfull = (wrusedw == depth-1);
|
| H A D | fifo.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
22 output wrfull; port
75 assign wrfull = (wrusedw == depth-1);
|
| H A D | fifo_1c_1k.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
20 output wrfull; port
76 assign wrfull = (wrusedw == depth-1);
|
| H A D | fifo_1k.v | 14 output wrfull, port
21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
| H A D | fifo_2k.v | 14 output wrfull, port
21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
| H A D | fifo_4k.v | 14 output wrfull, port
21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
| H A D | fifo_4k_18.v | 7 output wrfull, port
22 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
|
| H A D | fifo_1c_4k.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
20 output wrfull; port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/ |
| H A D | tx_buffer.v | 87 .wrfull ( ),
|
| H A D | rx_buffer.v | 93 .wrfull ( rx_full ),
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/inband_lib/ |
| H A D | rx_buffer_inband.v | 104 .wrfull ( ),
|
| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_altera_lpm.v | 6064 wrfull,
6094 output wrfull; port
6467 assign wrfull = w_wrfull;
6501 wrfull,
6534 output wrfull; port
6571 .wrfull (w_wrfull_a),
6592 assign wrfull = w_wrfull_a;
|