| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/ |
| H A D | fifo_1kx16.v | 41 wrreq,
52 input wrreq; port
74 .wrreq (wrreq),
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| H A D | fifo_4kx16_dc.v | 42 wrreq,
54 input wrreq; port
77 .wrreq (wrreq),
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| H A D | fifo_4k_18.v | 45 wrreq,
57 input wrreq; port
80 .wrreq (wrreq),
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| H A D | fifo_1kx16_bb.v | 36 wrreq,
47 input wrreq; port
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| H A D | fifo_2k_bb.v | 33 wrreq,
45 input wrreq; port
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| H A D | fifo_4k_bb.v | 33 wrreq,
45 input wrreq; port
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| H A D | fifo_4kx16_dc_bb.v | 37 wrreq,
49 input wrreq; port
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| H A D | fifo_1kx16_inst.v | 6 .wrreq ( wrreq_sig ),
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| H A D | fifo_4kx16_dc_inst.v | 7 .wrreq ( wrreq_sig ),
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| H A D | fifo_1kx16.bsf | 36 (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
37 (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
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| H A D | fifo_4kx16_dc.bsf | 36 (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
37 (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
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| H A D | fifo_1kx16.inc | 22 wrreq
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| H A D | fifo_4kx16_dc.inc | 23 wrreq
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| H A D | fifo_1kx16.cmp | 23 wrreq : IN STD_LOGIC ;
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| H A D | fifo_4kx16_dc.cmp | 24 wrreq : IN STD_LOGIC ;
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/models/ |
| H A D | fifo_1c_4k.v | 3 module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
11 input wrreq; port
48 if(wrreq)
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| H A D | fifo_1c_2k.v | 3 module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
11 input wrreq; port
48 if(wrreq)
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| H A D | fifo.v | 3 module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
13 input wrreq; port
47 if(wrreq)
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| H A D | fifo_1c_1k.v | 3 module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
11 input wrreq; port
48 if(wrreq)
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| H A D | fifo_1k.v | 5 input wrreq, port
20 ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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| H A D | fifo_2k.v | 5 input wrreq, port
20 ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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| H A D | fifo_4k.v | 5 input wrreq, port
20 ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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| H A D | fifo_4k_18.v | 5 input wrreq, port
21 ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/inband_lib/ |
| H A D | rx_buffer_inband.v | 100 .wrreq ( WR ),
180 .wrreq ( ~rx_full[i] & wr),
197 .wrreq ( rx_WR & rx_WR_enabled),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/ |
| H A D | tx_buffer.v | 85 .wrreq ( wr_reg & ~write_count[8] ),
|