| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/models/ |
| H A D | fifo_1c_2k.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
22 output [10:0] wrusedw; port
35 reg [10:0] wrusedw; register
70 wrusedw <= #1 wrptr - rdptr;
75 assign wrempty = (wrusedw == 0);
76 assign wrfull = (wrusedw == depth-1);
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| H A D | fifo_1c_1k.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
22 output [9:0] wrusedw; port
35 reg [9:0] wrusedw; register
70 wrusedw <= #1 wrptr - rdptr;
75 assign wrempty = (wrusedw == 0);
76 assign wrfull = (wrusedw == depth-1);
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| H A D | fifo.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
24 output reg [addr_bits-1:0] wrusedw; port
69 wrusedw <= #1 wrptr - rdptr;
74 assign wrempty = (wrusedw == 0);
75 assign wrfull = (wrusedw == depth-1);
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| H A D | fifo_1c_4k.v | 4 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
22 output [7:0] wrusedw; port
35 reg [7:0] wrusedw; register
70 wrusedw <= #1 wrptr - rdptr;
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| H A D | fifo_1k.v | 16 output [9:0] wrusedw port
21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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| H A D | fifo_2k.v | 16 output [10:0] wrusedw port
21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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| H A D | fifo_4k.v | 16 output [11:0] wrusedw port
21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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| H A D | fifo_4k_18.v | 9 output [11:0] wrusedw, port
22 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/ |
| H A D | fifo_4kx16_dc.v | 47 wrusedw);
59 output [11:0] wrusedw; port
67 wire [11:0] wrusedw = sub_wire1[11:0]; net
80 .wrusedw (sub_wire1),
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| H A D | fifo_4k_18.v | 50 wrusedw);
62 output [11:0] wrusedw; port
70 wire [11:0] wrusedw = sub_wire1[11:0]; net
83 .wrusedw (sub_wire1),
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| H A D | fifo_2k_bb.v | 42 wrusedw)/* synthesis synthesis_clearbox = 1 */;
54 output [10:0] wrusedw; port
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| H A D | fifo_4k_bb.v | 42 wrusedw)/* synthesis synthesis_clearbox = 1 */;
54 output [11:0] wrusedw; port
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| H A D | fifo_4kx16_dc_bb.v | 42 wrusedw);
54 output [11:0] wrusedw; port
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| H A D | fifo_4kx16_dc_inst.v | 12 .wrusedw ( wrusedw_sig )
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| H A D | fifo_4kx16_dc.bsf | 78 (text "wrusedw[11..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
79 (text "wrusedw[11..0]" (rect 63 66 132 79)(font "Arial" (font_size 8)))
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| H A D | fifo_4kx16_dc.inc | 31 wrusedw[11..0]
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| H A D | fifo_4kx16_dc.cmp | 29 wrusedw : OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
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| H A D | fifo_2k.v | 3025 wrusedw) /* synthesis synthesis_clearbox=1 */
3037 output [10:0] wrusedw; port
3211 wrusedw = wire_wrusedw_sub_result;
3230 wrusedw)/* synthesis synthesis_clearbox = 1 */;
3242 output [10:0] wrusedw; port
3250 wire [10:0] wrusedw = sub_wire1[10:0]; net
3263 .wrusedw (sub_wire1),
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| H A D | fifo_4k.v | 3177 wrusedw) /* synthesis synthesis_clearbox=1 */
3189 output [11:0] wrusedw; port
3363 wrusedw = wire_wrusedw_sub_result;
3382 wrusedw)/* synthesis synthesis_clearbox = 1 */;
3394 output [11:0] wrusedw; port
3402 wire [11:0] wrusedw = sub_wire1[11:0]; net
3415 .wrusedw (sub_wire1),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/inband_lib/ |
| H A D | rx_buffer_inband.v | 63 wire [11:0] wrusedw; net
105 .wrusedw ( wrusedw ) );
108 assign have_space = (wrusedw < 12'd760);
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/ |
| H A D | tx_buffer.v | 89 .wrusedw ( txfifolevel ),
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| H A D | rx_buffer.v | 95 .wrusedw ( ),
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| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_altera_lpm.v | 6068 wrusedw,
6098 output [lpm_widthu-1:0] wrusedw; port
6471 assign wrusedw = w_wrusedw;
6505 wrusedw,
6538 output [lpm_widthu-1:0] wrusedw; port
6575 .wrusedw (w_wrusedw_a),
6596 assign wrusedw = w_wrusedw_a;
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