/dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/aarch64/ |
H A D | illegal-sve2.s | 33 addp z32.s, p0/m, z32.s, z0.s 70 bcax z32.d, z32.d, z0.d, z0.d 77 bsl z32.d, z32.d, z0.d, z0.d 84 bsl1n z32.d, z32.d, z0.d, z0.d 91 bsl2n z32.d, z32.d, z0.d, z0.d 184 faddp z32.h, p0/m, z32.h, z0.h 247 fmaxnmp z32.h, p0/m, z32.h, z0.h 254 fmaxp z32.h, p0/m, z32.h, z0.h 261 fminnmp z32.h, p0/m, z32.h, z0.h 268 fminp z32.h, p0/m, z32.h, z0.h [all …]
|
H A D | illegal-sve2.l | 11 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d' 13 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d' 19 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s' 21 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s' 28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h' 30 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h' 72 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesimc z32\.b,z0\.b' 259 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h' 1822 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z32\.b,#0' 1874 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqshlu z32\.b,p0/m,z32\.b,#0' [all …]
|
H A D | illegal-bfloat16.s | 17 bfmlalt z32.s, z0.h, z0.h 18 bfmlalt z0.s, z32.h, z0.h 19 bfmlalt z0.s, z0.h, z32.h 23 bfmlalt z32.s, z0.h, z0.h[0] 24 bfmlalt z0.s, z32.h, z0.h[0] 28 bfmlalb z32.s, z0.h, z0.h 29 bfmlalb z0.s, z32.h, z0.h 30 bfmlalb z0.s, z0.h, z32.h 34 bfmlalb z32.s, z0.h, z0.h[0] 35 bfmlalb z0.s, z32.h, z0.h[0]
|
H A D | illegal-bfloat16.l | 28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h' 30 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\… 36 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]' 42 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h' 48 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
|
/dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/aarch64/ |
H A D | illegal-sve2.s | 33 addp z32.s, p0/m, z32.s, z0.s 70 bcax z32.d, z32.d, z0.d, z0.d 77 bsl z32.d, z32.d, z0.d, z0.d 84 bsl1n z32.d, z32.d, z0.d, z0.d 91 bsl2n z32.d, z32.d, z0.d, z0.d 184 faddp z32.h, p0/m, z32.h, z0.h 247 fmaxnmp z32.h, p0/m, z32.h, z0.h 254 fmaxp z32.h, p0/m, z32.h, z0.h 261 fminnmp z32.h, p0/m, z32.h, z0.h 268 fminp z32.h, p0/m, z32.h, z0.h [all …]
|
H A D | illegal-sve2.l | 11 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d' 13 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d' 19 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s' 21 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s' 28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h' 30 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h' 72 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesimc z32\.b,z0\.b' 259 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h' 1822 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z32\.b,#0' 1874 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqshlu z32\.b,p0/m,z32\.b,#0' [all …]
|
H A D | illegal-bfloat16.s | 17 bfmlalt z32.s, z0.h, z0.h 18 bfmlalt z0.s, z32.h, z0.h 19 bfmlalt z0.s, z0.h, z32.h 23 bfmlalt z32.s, z0.h, z0.h[0] 24 bfmlalt z0.s, z32.h, z0.h[0] 28 bfmlalb z32.s, z0.h, z0.h 29 bfmlalb z0.s, z32.h, z0.h 30 bfmlalb z0.s, z0.h, z32.h 34 bfmlalb z32.s, z0.h, z0.h[0] 35 bfmlalb z0.s, z32.h, z0.h[0]
|
H A D | illegal-bfloat16.l | 28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h' 30 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\… 36 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]' 42 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h' 48 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
|
/dports/devel/binutils/binutils-2.37/gas/testsuite/gas/aarch64/ |
H A D | illegal-sve2.s | 33 addp z32.s, p0/m, z32.s, z0.s 70 bcax z32.d, z32.d, z0.d, z0.d 77 bsl z32.d, z32.d, z0.d, z0.d 84 bsl1n z32.d, z32.d, z0.d, z0.d 91 bsl2n z32.d, z32.d, z0.d, z0.d 184 faddp z32.h, p0/m, z32.h, z0.h 247 fmaxnmp z32.h, p0/m, z32.h, z0.h 254 fmaxp z32.h, p0/m, z32.h, z0.h 261 fminnmp z32.h, p0/m, z32.h, z0.h 268 fminp z32.h, p0/m, z32.h, z0.h [all …]
|
H A D | illegal-sve2.l | 11 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d' 13 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d' 19 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s' 21 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s' 28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h' 30 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h' 72 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesimc z32\.b,z0\.b' 259 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h' 1822 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z32\.b,#0' 1874 [^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqshlu z32\.b,p0/m,z32\.b,#0' [all …]
|
H A D | illegal-bfloat16.s | 17 bfmlalt z32.s, z0.h, z0.h 18 bfmlalt z0.s, z32.h, z0.h 19 bfmlalt z0.s, z0.h, z32.h 23 bfmlalt z32.s, z0.h, z0.h[0] 24 bfmlalt z0.s, z32.h, z0.h[0] 28 bfmlalb z32.s, z0.h, z0.h 29 bfmlalb z0.s, z32.h, z0.h 30 bfmlalb z0.s, z0.h, z32.h 34 bfmlalb z32.s, z0.h, z0.h[0] 35 bfmlalb z0.s, z32.h, z0.h[0]
|
H A D | illegal-bfloat16.l | 28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h' 30 [^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\… 36 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]' 42 [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h' 48 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
|
/dports/math/gap/gap-4.11.0/tst/testinstall/ |
H A D | ffeconway.tst | 123 29+z31+2z32+z33+z34+2z35+2z37+2z38+z39+2z40+z43+z59 154 z31+z32+2z33+2z34+z35+z37+z38+2z39+z40+2z43+2z59, 9+9z+6z3, 255+87z, 180 31+z32+2z33+2z34+z35+z37+z38+2z39+z40+2z43+2z59, 9+8z+6z3, 255+86z, 193 +z30+z31+z32+z35+z37+z38+z40+z47+z48+z50+z51+z56+z58+z62+z63+z67, 253 27+2z28+2z29+2z30+z32, 316 +z30+z31+z32+z35+z37+z38+z40+z47+z48+z50+z51+z56+z58+z62+z63+z67, 397 +2z25+2z26+2z28+z29+2z30+2z32+z33+z34+z36+2z38+z39, 506 z30+2z31+2z32+z33+z37+z38+2z41, 597 +z32+z34+z38+z39+z41+z43+z50+z52+z56+z57, 644 +z30+2z31+2z32, [all …]
|
/dports/audio/praat/praat-6.2.03/external/gsl/ |
H A D | gsl_specfunc__bessel_olver.c | 559 const double z32 = rz*rz*rz; 560 const double z92 = z32*z32*z32; 564 const double term4 = 5.0/55296.0*t2*(81.0 - 462.0*t2 + 385.0*t2*t2)/z32; 586 const double z32 = rz*rz*rz; 587 const double z92 = z32*z32*z32; 591 const double term4 = 5.0/55296.0*t2*(81.0 + 462.0*t2 + 385.0*t2*t2)/z32; 708 double z32 = rz*rz*rz; 709 double z92 = z3*z32; 714 double term5 = -7.0/19906560.0*t*t2*(30375.0 - 369603.0*t2 + 765765.0*t4 - 425425.0*t6)/z32; 740 const double z32 = rz*rz*rz; [all …]
|
/dports/math/gsl/gsl-2.7/specfunc/ |
H A D | bessel_olver.c | 559 const double z32 = rz*rz*rz; in olver_B1() local 560 const double z92 = z32*z32*z32; in olver_B1() 564 const double term4 = 5.0/55296.0*t2*(81.0 - 462.0*t2 + 385.0*t2*t2)/z32; in olver_B1() 586 const double z32 = rz*rz*rz; in olver_B1() local 587 const double z92 = z32*z32*z32; in olver_B1() 591 const double term4 = 5.0/55296.0*t2*(81.0 + 462.0*t2 + 385.0*t2*t2)/z32; in olver_B1() 708 double z32 = rz*rz*rz; in olver_A2() local 709 double z92 = z3*z32; in olver_A2() 714 double term5 = -7.0/19906560.0*t*t2*(30375.0 - 369603.0*t2 + 765765.0*t4 - 425425.0*t6)/z32; in olver_A2() 740 const double z32 = rz*rz*rz; in olver_A2() local [all …]
|
/dports/math/octave-forge-nnet/nnet/doc/latex/asymptote/ |
H A D | mlp4-2-3.asy | 53 pair z32=(44,31); 54 draw(z31--z32,Arrow); 70 pair z32=(44,51); 71 draw(z31--z32,Arrow); 95 pair z32=(84,21); 96 draw(z31--z32,Arrow);
|
/dports/science/gabedit/GabeditSrc251_300720/src/SemiEmpirical/ |
H A D | AtomSE.c | 37 gdouble x12, x32, y12, y32, z12, z32, l12, l32, dp; in getAngleSE() local 44 z32 = C3[ 2 ] - C2[ 2 ]; in getAngleSE() 47 l32 = sqrt( x32 * x32 + y32 * y32 + z32 * z32 ); in getAngleSE() 56 dp = ( x12 * x32 + y12 * y32 + z12 * z32 ) / (l12 * l32 ); in getAngleSE()
|
/dports/science/gabedit/GabeditSrc251_300720/src/MolecularMechanics/ |
H A D | Atom.c | 37 gdouble x12, x32, y12, y32, z12, z32, l12, l32, dp; in getAngle() local 44 z32 = C3[ 2 ] - C2[ 2 ]; in getAngle() 47 l32 = sqrt( x32 * x32 + y32 * y32 + z32 * z32 ); in getAngle() 56 dp = ( x12 * x32 + y12 * y32 + z12 * z32 ) / (l12 * l32 ); in getAngle()
|
/dports/science/elk/elk-7.2.42/src/ |
H A D | genpmatk.f90 | 106 z31=gvmt(i,3)*z1; z32=gvmt(i,3)*z2 107 zfmt2(i,1,1)=cmplx(aimag(z32),-dble(z32),8)-z21 109 zfmt2(i,2,1)=z11-z32
|
/dports/astro/libgal/libgal-0.5.0/sgp4/ |
H A D | gal_dscom.c | 231 double *z32, in gal_dscom() 341 *z32 = 24.0 * x1 * x2 - 6.0 * x3 * x4 ; in gal_dscom() 344 *z2 = 6.0 * ( a1 * a3 + a2 * a4 ) + *z32 * (*emsq) ; in gal_dscom() 355 *z2 = *z2 + *z2 + betasq * (*z32) ; in gal_dscom() 387 *sz32 = *z32 ; in gal_dscom() 430 *xgh2 = 2.0 * (*s4) * (*z32) ; in gal_dscom()
|
/dports/audio/py-zita-jacktools/zita-jacktools-1.5.3/source/ |
H A D | nmeterdsp.cc | 268 float x, zhp, z11, z12, z21, z22, z31, z32; in process() local 281 z32 = _z32; in process() 294 x -= _a31 * z31 + _a32 * z32; in process() 295 *out++ = _b30 * x + _b31 * z31 + _b32 * z32; in process() 296 z32 = z31; in process() 306 _z32 = z32; in process()
|
/dports/astro/py-pykep/pykep-2.6/src/third_party/cspice/ |
H A D | zzdscm.c | 31 doublereal *z31, doublereal *z32, doublereal *z33, doublereal *zmol, in zzdscm_() argument 453 *z32 = x1 * 24. * x2 - x3 * 6. * x4; in zzdscm_() 456 *z2 = (a1 * a3 + a2 * a4) * 6. + *z32 * *emsq; in zzdscm_() 467 *z2 = *z2 + *z2 + betasq * *z32; in zzdscm_() 497 *sz32 = *z32; in zzdscm_() 539 *xgh2 = *s4 * 2. * *z32; in zzdscm_()
|
/dports/astro/pykep/pykep-2.6/src/third_party/cspice/ |
H A D | zzdscm.c | 31 doublereal *z31, doublereal *z32, doublereal *z33, doublereal *zmol, in zzdscm_() argument 453 *z32 = x1 * 24. * x2 - x3 * 6. * x4; in zzdscm_() 456 *z2 = (a1 * a3 + a2 * a4) * 6. + *z32 * *emsq; in zzdscm_() 467 *z2 = *z2 + *z2 + betasq * *z32; in zzdscm_() 497 *sz32 = *z32; in zzdscm_() 539 *xgh2 = *s4 * 2. * *z32; in zzdscm_()
|
/dports/science/xcrysden/xcrysden-1.6.2/Tcl/ |
H A D | selection.tcl | 306 set z32 [expr $select(Z2) - $select(Z3)] 307 set d32 [expr sqrt( $x32 * $x32 + $y32 * $y32 + $z32 * $z32)] 309 set ab [expr $x21 * $x32 + $y21 * $y32 + $z21 * $z32] 373 set z32 [expr $select(Z2) - $select(Z3)] 383 set sd32 [expr $x32 * $x32 + $y32 * $y32 + $z32 * $z32] 384 set la [expr ( $x21 * $x32 + $y21 * $y32 + $z21 * $z32 ) / $sd32 ] 385 set lb [expr ( $x34 * $x32 + $y34 * $y32 + $z34 * $z32 ) / $sd32 ] 389 set zar [expr $z21 - $la * $z32] 394 set zbr [expr $z34 - $lb * $z32]
|
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/VE/ |
H A D | va_arg.ll | 49 %p4.z32 = zext i16 %p4 to i32 50 …, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.4, i64 0, i64 0), i32 %p4.z32) 51 %p5.z32 = zext i8 %p5 to i32 52 …, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str.5, i64 0, i64 0), i32 %p5.z32)
|