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Searched refs:AR_PHY_TIMING5_CYCPWR_THR1_ENABLE (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300phy.h216 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001 macro
H A Dar9300_misc.c1438 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); in ar9300_dma_reg_dump()
H A Dar9300_reset.c3789 …REG_WRITE(ah, AR_PHY_TIMING5, OS_REG_READ(ah,AR_PHY_TIMING5) & ~AR_PHY_TIMING5_CYCPWR_THR1_ENABLE); in ar9300_init_cal_internal()