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Searched refs:BIT_5 (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/netif/msk/
H A Dif_mskreg.h184 #define BIT_5 (1 << 5) macro
302 #define PCI_EXT_PATCH_1 BIT_5
809 #define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
1108 #define BMU_FIFO_ENA BIT_5 /* Enable FIFO */
1166 #define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */
1230 #define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5
1824 #define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */
1907 #define GMR_FS_MII_ERR BIT_5 /* MII Error */
1999 #define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */
2026 #define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5
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/dragonfly/sys/dev/netif/re/
H A Dre.c6425 data16 |= BIT_5; in re_hw_start_unlock()
6511 data16 |= BIT_5; in re_hw_start_unlock()
7427 data16 &= ~(BIT_5 | BIT_4); in re_hw_start_unlock_8125()
7448 data16 |= (BIT_4 | BIT_5); in re_hw_start_unlock_8125()
13400 if (PhyRegValue & BIT_5) { in re_set_phy_mcu_8168e_2()
14795 if (PhyRegValue & BIT_5) { in re_set_phy_mcu_8168evl_1()
26614 Data |= BIT_5; in re_hw_phy_config()
29349 PhyRegValue |= (BIT_5); in re_hw_phy_config()
29388 PhyRegValue |= (BIT_5); in re_hw_phy_config()
29403 PhyRegValue |= (BIT_5); in re_hw_phy_config()
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H A Dre.h1000 BIT_5 = (1 << 5), enumerator