/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 510 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optLEAALU() 514 if (BaseReg == IndexReg) in optLEAALU() 516 std::swap(BaseReg, IndexReg); in optLEAALU() 519 if (BaseReg == IndexReg) in optLEAALU() 575 if (BaseReg != 0) in optTwoAddrLEA() 576 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optTwoAddrLEA() 589 if (DestReg != BaseReg) in optTwoAddrLEA() 620 .addReg(BaseReg); in optTwoAddrLEA() 763 if (BaseReg != 0) in processInstrForSlow3OpLEA() 764 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in processInstrForSlow3OpLEA() [all …]
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H A D | X86InsertPrefetch.cpp | 84 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local 86 return (BaseReg == 0 || in IsMemOpCompatibleWithPrefetch() 87 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) || in IsMemOpCompatibleWithPrefetch() 88 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) && in IsMemOpCompatibleWithPrefetch()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCRegisterInfo.cpp | 46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local 51 .addReg(BaseReg) in replaceFrameIndex() 60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in replaceFrameIndex() 61 if (!BaseReg) { in replaceFrameIndex() 66 BaseReg = in replaceFrameIndex() 68 assert(BaseReg && "Register scavenging failed."); in replaceFrameIndex() 69 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in replaceFrameIndex() 73 RS->setRegUsed(BaseReg); in replaceFrameIndex() 77 .addReg(BaseReg, RegState::Define) in replaceFrameIndex() 95 .addReg(BaseReg, KillState) in replaceFrameIndex() [all …]
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H A D | ARCOptAddrMode.cpp | 101 MachineOperand &Incr, unsigned BaseReg); 105 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg, 297 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local 307 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions() 315 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) { in canJoinInstructions() 353 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument 459 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local 473 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LocalStackSlotAllocation.cpp | 272 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument 281 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg() 345 Register BaseReg; in insertFrameReferenceRegisters() local 388 if (BaseReg.isValid() && in insertFrameReferenceRegisters() 389 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters() 391 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters() 407 BaseReg, CandBaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters() 422 << " into " << printReg(BaseReg, TRI) << '\n'); in insertFrameReferenceRegisters() 431 assert(BaseReg && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters() 435 TRI->resolveFrameIndex(MI, BaseReg, Offset); in insertFrameReferenceRegisters() [all …]
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H A D | ImplicitNullChecks.cpp | 378 const Register BaseReg = AddrMode.BaseReg, ScaledReg = AddrMode.ScaledReg; in isSuitableMemoryOp() local 383 if (BaseReg != PointerReg && ScaledReg != PointerReg) in isSuitableMemoryOp() 389 if ((BaseReg && in isSuitableMemoryOp() 390 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) || in isSuitableMemoryOp() 449 if (CalculateDisplacementFromAddrMode(BaseReg, 1)) in isSuitableMemoryOp() 459 if ((BaseReg && BaseReg != PointerReg && !BaseRegIsConstVal) || in isSuitableMemoryOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ThumbRegisterInfo.cpp | 133 if (BaseReg == ARM::SP && in emitThumbRegPlusImmInReg() 145 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg() 157 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg() 285 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate() 297 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate() 303 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate() 306 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate() 320 if (DestReg == BaseReg) { in emitThumbRegPlusImmediate() 380 MIB.addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmediate() 386 BaseReg = DestReg; in emitThumbRegPlusImmediate() [all …]
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H A D | Thumb2InstrInfo.cpp | 296 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate() 298 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate() 308 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate() 330 .addReg(BaseReg) in emitT2RegPlusImmediate() 342 .addReg(BaseReg) in emitT2RegPlusImmediate() 355 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate() 358 .addReg(BaseReg) in emitT2RegPlusImmediate() 361 BaseReg = ARM::SP; in emitT2RegPlusImmediate() 365 assert((DestReg != ARM::SP || BaseReg == ARM::SP) && in emitT2RegPlusImmediate() 373 .addReg(BaseReg) in emitT2RegPlusImmediate() [all …]
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H A D | ARMBaseRegisterInfo.cpp | 681 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local 682 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister() 684 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister() 690 return BaseReg; in materializeFrameBaseRegister() 693 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex() argument 712 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex() 715 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this); in resolveFrameIndex() 722 Register BaseReg, in isFrameOffsetLegal() argument 765 NumBits = (BaseReg == ARM::SP ? 8 : 5); in isFrameOffsetLegal()
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H A D | Thumb2SizeReduction.cpp | 497 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local 498 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore() 504 if (MO.getReg() == BaseReg) { in ReduceLoadStore() 527 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local 529 if (MO.getReg() == BaseReg) in ReduceLoadStore() 535 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local 536 if (BaseReg != ARM::SP) in ReduceLoadStore() 548 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local 549 if (BaseReg == ARM::SP && in ReduceLoadStore() 554 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
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H A D | ARMLoadStoreOptimizer.cpp | 1770 Register BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local 1778 bool Errata602117 = EvenReg == BaseReg && in FixInvalidRegPairOp() 1811 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp() 1819 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp() 1840 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) { in FixInvalidRegPairOp() 1841 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp() 1856 if (EvenReg == BaseReg) in FixInvalidRegPairOp() 2315 BaseReg = Op0->getOperand(1).getReg(); in CanFormLdStDWord() 2415 Register BaseReg, PredReg; in RescheduleOps() local 2437 .addReg(BaseReg); in RescheduleOps() [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LoadStoreOpt.h | 40 Register BaseReg; 46 Register getBase() { return BaseReg; } in getBase() 47 Register getBase() const { return BaseReg; } in getBase() 50 void setBase(Register NewBase) { BaseReg = NewBase; } in setBase()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 1302 if (BaseReg != 0 && in CheckBaseRegAndIndexRegAndScale() 1303 !(BaseReg == X86::RIP || BaseReg == X86::EIP || in CheckBaseRegAndIndexRegAndScale() 1323 if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) || in CheckBaseRegAndIndexRegAndScale() 1333 (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP && in CheckBaseRegAndIndexRegAndScale() 1334 BaseReg != X86::SI && BaseReg != X86::DI))) { in CheckBaseRegAndIndexRegAndScale() 1366 if ((BaseReg != X86::BX && BaseReg != X86::BP) || in CheckBaseRegAndIndexRegAndScale() 1376 (BaseReg == X86::RIP || BaseReg == X86::EIP)) { in CheckBaseRegAndIndexRegAndScale() 2591 BaseReg = 0; in parseIntelOperand() 2596 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP && in parseIntelOperand() 2622 if ((BaseReg == X86::SI || BaseReg == X86::DI) && in parseIntelOperand() [all …]
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H A D | X86Operand.h | 65 unsigned BaseReg; member 145 if (Mem.BaseReg) in print() 146 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg); in print() 195 return Mem.BaseReg; in getMemBaseReg() 335 return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP; in isSibMem() 723 Res->Mem.BaseReg = 0; 741 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, 749 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) && 758 Res->Mem.BaseReg = BaseReg;
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kISelDAGToDAG.cpp | 67 SDValue BaseReg; member 145 BaseReg = Reg; in setBaseReg() 155 if (BaseReg.getNode()) in dump() 156 BaseReg.getNode()->dump(); in dump() 423 AM.BaseReg = N; in matchAddressBase() 498 AM.BaseReg.getNode() == nullptr && doesDispFitFI(AM)) { in matchAddressRecursively() 554 AM.BaseReg = N.getOperand(0); in matchADD() 735 Base = AM.BaseReg; in SelectARID() 795 Index = AM.BaseReg; in SelectARII() 797 Base = AM.BaseReg; in SelectARII() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64StorePairSuppress.cpp | 160 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local 161 if (PrevBaseReg == BaseReg) { in runOnMachineFunction() 170 PrevBaseReg = BaseReg; in runOnMachineFunction()
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H A D | AArch64FalkorHWPFFix.cpp | 214 Register BaseReg; member 643 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local 644 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP) in getLoadInfo() 649 LI.BaseReg = BaseReg; in getLoadInfo() 660 unsigned Base = TRI->getEncodingValue(LI.BaseReg); in getTag() 754 NewLdI.BaseReg = ScratchReg; in runOnLoop() 771 .addReg(LdI.BaseReg) in runOnLoop() 784 TII->get(AArch64::ORRXrs), LdI.BaseReg) in runOnLoop()
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H A D | AArch64LoadStoreOptimizer.cpp | 1342 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingStore() 1763 if (BaseReg == MIBaseReg) { in findMatchingInsn() 1938 if (!ModifiedRegUnits.available(BaseReg)) { in findMatchingInsn() 2069 if (MI.getOperand(0).getReg() != BaseReg || in isMatchingUpdateInsn() 2070 MI.getOperand(1).getReg() != BaseReg) in isMatchingUpdateInsn() 2124 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnForward() 2166 if (!ModifiedRegUnits.available(BaseReg) || in findMatchingUpdateInsnForward() 2167 !UsedRegUnits.available(BaseReg) || in findMatchingUpdateInsnForward() 2195 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnBackward() 2241 if (!ModifiedRegUnits.available(BaseReg) || in findMatchingUpdateInsnBackward() [all …]
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H A D | AArch64RegisterInfo.h | 113 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, 117 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | LoadStoreOpt.cpp | 87 Register BaseReg; in getPointerInfo() local 88 if (!mi_match(Ptr, MRI, m_GPtrAdd(m_Reg(BaseReg), m_Reg(PtrAddRHS)))) { in getPointerInfo() 93 Info.setBase(BaseReg); in getPointerInfo() 206 Register BaseReg; in instMayAlias() local 210 m_GPtrAdd(m_Reg(BaseReg), m_ICst(Offset)))) { in instMayAlias() 211 BaseReg = LS->getPointerReg(); in instMayAlias() 217 return {LS->isVolatile(), LS->isAtomic(), BaseReg, in instMayAlias() 730 Register BaseReg; in mergeTruncStore() local 733 m_GPtrAdd(m_Reg(BaseReg), m_ICst(LastOffset)))) { in mergeTruncStore() 734 BaseReg = LastStore.getPointerReg(); in mergeTruncStore() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
H A D | LanaiAsmParser.cpp | 129 unsigned BaseReg; member 171 return Mem.BaseReg; in getMemBaseReg() 614 Op->Mem.BaseReg = 0; in MorphToMemImm() 622 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegReg() 626 Op->Mem.BaseReg = BaseReg; in MorphToMemRegReg() 634 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegImm() 638 Op->Mem.BaseReg = BaseReg; in MorphToMemRegImm() 903 unsigned BaseReg = 0; in parseMemoryOperand() local 957 BaseReg = Op->getReg(); in parseMemoryOperand() 983 if (!BaseReg || Lexer.isNot(AsmToken::RBrac)) in parseMemoryOperand() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelDAGToDAG.cpp | 27 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg, 79 SDValue &BaseReg, in SelectGlobalValueVariableOffset() argument 82 BaseReg = Addr; in SelectGlobalValueVariableOffset()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVRegisterInfo.h | 58 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, 64 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.h | 49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local 52 if (Op.isReg() && Op.getReg() == BaseReg) in isLDMBaseRegInList()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
H A D | VEAsmParser.cpp | 1290 MCRegister BaseReg; in parseMEMOperand() local 1291 if (parseRegister(BaseReg, S, E)) in parseMEMOperand() 1300 ? VEOperand::MorphToMEMrii(BaseReg, IndexValue, std::move(Offset)) in parseMEMOperand() 1301 : VEOperand::MorphToMEMrri(BaseReg, IndexReg, std::move(Offset))); in parseMEMOperand() 1320 MCRegister BaseReg; in parseMEMAsOperand() local 1339 if (parseRegister(BaseReg, S, E)) in parseMEMAsOperand() 1358 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand() 1364 if (BaseReg != VE::NoRegister) in parseMEMAsOperand() 1372 if (parseRegister(BaseReg, S, E)) in parseMEMAsOperand() 1378 if (parseRegister(BaseReg, S, E)) in parseMEMAsOperand() [all …]
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