Searched refs:GLD1_IMM_MERGE_ZERO (Results 1 – 3 of 3) sorted by relevance
389 GLD1_IMM_MERGE_ZERO, enumerator
2598 MAKE_CASE(AArch64ISD::GLD1_IMM_MERGE_ZERO) in getTargetNodeName()5587 case AArch64ISD::GLD1_IMM_MERGE_ZERO: in getSignExtendedGatherOpcode()17785 case AArch64ISD::GLD1_IMM_MERGE_ZERO: in performSVEAndCombine()21002 Opc <= AArch64ISD::GLD1_IMM_MERGE_ZERO) || in performGLD1Combine()23227 if (Opcode == AArch64ISD::GLD1_IMM_MERGE_ZERO || in performGatherLoadCombine()23232 Opcode = (Opcode == AArch64ISD::GLD1_IMM_MERGE_ZERO) in performGatherLoadCombine()23236 Opcode = (Opcode == AArch64ISD::GLD1_IMM_MERGE_ZERO) in performGatherLoadCombine()23362 case AArch64ISD::GLD1_IMM_MERGE_ZERO: in performSignExtendInRegCombine()23960 case AArch64ISD::GLD1_IMM_MERGE_ZERO: in PerformDAGCombine()24089 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_IMM_MERGE_ZERO); in PerformDAGCombine()
75 def AArch64ld1_gather_imm_z : SDNode<"AArch64ISD::GLD1_IMM_MERGE_ZERO", SDT_AArch64…