Searched refs:HCLK (Results 1 – 13 of 13) sorted by relevance
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
34 HCLK nodes: these represent the clock gates on individual35 lines from the HCLK clock tree and the gate for individual38 Requires properties for the HCLK nodes:
200 - description: HCLK which used for host220 - description: HCLK which used for host253 - description: HCLK which used for host278 - description: HCLK which used for host298 - description: HCLK which used for host
27 "hclk" - HCLK which used for host (required)
77 - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
50 "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
25 #define HCLK 5 macro
27 #define HCLK 7 macro
24 #define HCLK 5 macro
27 #define HCLK 8 macro
3 #define HCLK 1 macro
65 - description: The HCLK AHB slave clock for the register access.
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */232 /* The PCLK domain uses HCLK right off */