/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 1357 SDValue Offset, ISD::MemIndexedMode AM); 1418 SDValue Offset, ISD::MemIndexedMode AM); 1427 getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, 1461 SDValue Offset, ISD::MemIndexedMode AM); 1464 MachineMemOperand *MMO, ISD::MemIndexedMode AM, 1475 SDValue Offset, ISD::MemIndexedMode AM); 1526 ISD::MemIndexedMode AM); 1546 ISD::MemIndexedMode AM); 1557 MachineMemOperand *MMO, ISD::MemIndexedMode AM, 1560 SDValue Offset, ISD::MemIndexedMode AM); [all …]
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H A D | SelectionDAGNodes.h | 1035 static const char* getIndexedModeName(ISD::MemIndexedMode AM); 2353 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, 2366 ISD::MemIndexedMode getAddressingMode() const { 2387 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, 2415 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, 2449 ISD::MemIndexedMode AM, EVT MemVT, 2503 ISD::MemIndexedMode getAddressingMode() const { 2554 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, 2657 ISD::MemIndexedMode AM, EVT MemVT, 2676 ISD::MemIndexedMode getAddressingMode() const { [all …]
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H A D | ISDOpcodes.h | 1455 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enum
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H A D | BasicTTIImpl.h | 191 static ISD::MemIndexedMode getISDIndexedMode(TTI::MemIndexedMode M) { in getISDIndexedMode() 369 bool isIndexedLoadLegal(TTI::MemIndexedMode M, Type *Ty, in isIndexedLoadLegal() 375 bool isIndexedStoreLegal(TTI::MemIndexedMode M, Type *Ty, in isIndexedStoreLegal()
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H A D | TargetLowering.h | 3700 ISD::MemIndexedMode &/*AM*/, in getPreIndexedAddressParts() argument 3711 ISD::MemIndexedMode &/*AM*/, in getPostIndexedAddressParts() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.h | 110 ISD::MemIndexedMode &AM, 114 SDValue &Offset, ISD::MemIndexedMode &AM,
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H A D | AVRISelDAGToDAG.cpp | 133 ISD::MemIndexedMode AM = LD->getAddressingMode(); in selectIndexedLoad()
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H A D | AVRISelLowering.cpp | 1089 ISD::MemIndexedMode &AM, in getPreIndexedAddressParts() 1146 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 184 ISD::MemIndexedMode &AM,
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H A D | MSP430ISelDAGToDAG.cpp | 303 ISD::MemIndexedMode AM = LD->getAddressingMode(); in isValidIndexedLoad()
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H A D | MSP430ISelLowering.cpp | 1335 ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.h | 780 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const; 782 ISD::MemIndexedMode &AM, 785 SDValue &Offset, ISD::MemIndexedMode &AM,
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H A D | RISCVISelDAGToDAG.cpp | 757 ISD::MemIndexedMode AM = Ld->getAddressingMode(); in tryIndexedLoad()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | TargetTransformInfo.h | 1577 enum MemIndexedMode { enum 1586 bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const; 1589 bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const; 2078 virtual bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const = 0; 2079 virtual bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const = 0; 2764 bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const override { in isIndexedLoadLegal() 2767 bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const override { in isIndexedStoreLegal()
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H A D | TargetTransformInfoImpl.h | 844 bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, in isIndexedLoadLegal() 849 bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, in isIndexedStoreLegal()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 503 ISD::MemIndexedMode &AM, 510 SDValue &Offset, ISD::MemIndexedMode &AM,
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H A D | ARMISelDAGToDAG.cpp | 833 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetReg() 869 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImmPre() 889 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode2OffsetImm() 968 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectAddrMode3Offset() 1088 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); in SelectAddrMode6Offset() 1395 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) in SelectT2AddrModeImm8Offset() 1447 ISD::MemIndexedMode AM; in SelectT2AddrModeImm7Offset() 1591 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryARMIndexedLoad() 1671 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryT1IndexedLoad() 1697 ISD::MemIndexedMode AM = LD->getAddressingMode(); in tryT2IndexedLoad() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 1261 ISD::MemIndexedMode &AM, 1264 SDValue &Offset, ISD::MemIndexedMode &AM,
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | TargetTransformInfo.cpp | 1181 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode, in isIndexedLoadLegal() 1186 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode, in isIndexedStoreLegal()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 8588 ISD::MemIndexedMode AM) { in getIndexedLoad() 8721 ISD::MemIndexedMode AM) { in getIndexedStore() 8771 SDValue SelectionDAG::getLoadVP(ISD::MemIndexedMode AM, in getLoadVP() 8851 ISD::MemIndexedMode AM) { in getIndexedLoadVP() 8973 ISD::MemIndexedMode AM) { in getIndexedStoreVP() 9102 ISD::MemIndexedMode AM) { in getIndexedStridedLoadVP() 9122 ISD::MemIndexedMode AM, in getStridedStoreVP() 9225 ISD::MemIndexedMode AM) { in getIndexedStridedStoreVP() 9345 ISD::MemIndexedMode AM, in getMaskedLoad() 9378 ISD::MemIndexedMode AM) { in getIndexedMaskedLoad() [all …]
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H A D | SelectionDAGDumper.cpp | 525 const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) { in getIndexedModeName()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 292 ISD::MemIndexedMode &AM,
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H A D | HexagonISelDAGToDAG.cpp | 455 ISD::MemIndexedMode AM = LD->getAddressingMode(); in SelectLoad() 564 ISD::MemIndexedMode AM = ST->getAddressingMode(); in SelectStore()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAG.td | 1279 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1290 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1331 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1337 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 835 ISD::MemIndexedMode &AM,
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