/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVOptWInstrs.cpp | 351 case RISCV::SRAI: in isSignExtendingOpW() 362 case RISCV::ORI: in isSignExtendingOpW() 605 case RISCV::ADD: in getWOp() 607 case RISCV::LD: in getWOp() 608 case RISCV::LWU: in getWOp() 610 case RISCV::MUL: in getWOp() 614 case RISCV::SUB: in getWOp() 687 case RISCV::ADDW: Opc = RISCV::ADD; break; in stripWSuffixes() 688 case RISCV::ADDIW: Opc = RISCV::ADDI; break; in stripWSuffixes() 689 case RISCV::MULW: Opc = RISCV::MUL; break; in stripWSuffixes() [all …]
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H A D | RISCVInstrInfo.cpp | 609 RISCV::SW : RISCV::SD; in storeRegToStackSlot() 692 RISCV::LW : RISCV::LD; in loadRegFromStackSlot() 1324 case RISCV::ADD: return RISCV::PseudoCCADD; break; in getPredicatedOpcode() 1325 case RISCV::SUB: return RISCV::PseudoCCSUB; break; in getPredicatedOpcode() 1326 case RISCV::SLL: return RISCV::PseudoCCSLL; break; in getPredicatedOpcode() 1327 case RISCV::SRL: return RISCV::PseudoCCSRL; break; in getPredicatedOpcode() 1328 case RISCV::SRA: return RISCV::PseudoCCSRA; break; in getPredicatedOpcode() 1329 case RISCV::AND: return RISCV::PseudoCCAND; break; in getPredicatedOpcode() 1330 case RISCV::OR: return RISCV::PseudoCCOR; break; in getPredicatedOpcode() 1331 case RISCV::XOR: return RISCV::PseudoCCXOR; break; in getPredicatedOpcode() [all …]
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H A D | RISCVExpandPseudoInsts.cpp | 209 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break; in expandCCOp() 210 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break; in expandCCOp() 211 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break; in expandCCOp() 212 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break; in expandCCOp() 213 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break; in expandCCOp() 214 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break; in expandCCOp() 215 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break; in expandCCOp() 216 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break; in expandCCOp() 217 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break; in expandCCOp() 218 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break; in expandCCOp() [all …]
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H A D | RISCVRegisterInfo.cpp | 42 static_assert(RISCV::F31_H == RISCV::F0_H + 31, 45 static_assert(RISCV::F31_F == RISCV::F0_F + 31, 48 static_assert(RISCV::F31_D == RISCV::F0_D + 31, 119 for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++) in getReservedRegs() 308 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7, in lowerVSPILL() 310 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3, in lowerVSPILL() 312 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1, in lowerVSPILL() 385 static_assert(RISCV::sub_vrm1_7 == RISCV::sub_vrm1_0 + 7, in lowerVRELOAD() 387 static_assert(RISCV::sub_vrm2_3 == RISCV::sub_vrm2_0 + 3, in lowerVRELOAD() 389 static_assert(RISCV::sub_vrm4_1 == RISCV::sub_vrm4_0 + 1, in lowerVRELOAD() [all …]
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H A D | RISCVAsmPrinter.cpp | 242 case RISCV::KCFI_CHECK: in emitInstruction() 482 unsigned ScratchRegs[] = {RISCV::X6, RISCV::X7}; in LowerKCFI_CHECK() 493 if (Reg > RISCV::X31) in LowerKCFI_CHECK() 598 MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8), in EmitHwasanMemaccessSymbols() 612 MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0), in EmitHwasanMemaccessSymbols() 616 MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56), in EmitHwasanMemaccessSymbols() 650 MCInstBuilder(RISCV::ANDI).addReg(RISCV::X28).addReg(Reg).addImm(0xF), in EmitHwasanMemaccessSymbols() 667 MCInstBuilder(RISCV::ORI).addReg(RISCV::X6).addReg(Reg).addImm(0xF), in EmitHwasanMemaccessSymbols() 670 MCInstBuilder(RISCV::LBU).addReg(RISCV::X6).addReg(RISCV::X6).addImm(0), in EmitHwasanMemaccessSymbols() 737 MCInstBuilder(RISCV::SD).addReg(RISCV::X8).addReg(RISCV::X2).addImm(8 * in EmitHwasanMemaccessSymbols() [all …]
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H A D | RISCVMakeCompressible.cpp | 102 case RISCV::LW: in log2LdstWidth() 103 case RISCV::SW: in log2LdstWidth() 104 case RISCV::FLW: in log2LdstWidth() 105 case RISCV::FSW: in log2LdstWidth() 107 case RISCV::LD: in log2LdstWidth() 108 case RISCV::SD: in log2LdstWidth() 109 case RISCV::FLD: in log2LdstWidth() 110 case RISCV::FSD: in log2LdstWidth() 148 return Opcode == RISCV::LW || (!STI.is64Bit() && Opcode == RISCV::FLW) || in isCompressibleLoad() 149 Opcode == RISCV::LD || Opcode == RISCV::FLD; in isCompressibleLoad() [all …]
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H A D | RISCVMergeBaseOffset.cpp | 87 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC) in INITIALIZE_PASS() 333 case RISCV::ADD: in detectAndFoldOffset() 379 case RISCV::LB: in foldIntoMemoryOps() 380 case RISCV::LH: in foldIntoMemoryOps() 381 case RISCV::LW: in foldIntoMemoryOps() 382 case RISCV::LBU: in foldIntoMemoryOps() 385 case RISCV::LD: in foldIntoMemoryOps() 389 case RISCV::SB: in foldIntoMemoryOps() 390 case RISCV::SH: in foldIntoMemoryOps() 391 case RISCV::SW: in foldIntoMemoryOps() [all …]
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H A D | RISCVExpandAtomicPseudoInsts.cpp | 159 return RISCV::LR_W; in getLRForRMW32() 162 return RISCV::LR_W; in getLRForRMW32() 165 return RISCV::LR_W; in getLRForRMW32() 168 return RISCV::LR_W; in getLRForRMW32() 181 return RISCV::SC_W; in getSCForRMW32() 183 return RISCV::SC_W; in getSCForRMW32() 203 return RISCV::LR_D; in getLRForRMW64() 209 return RISCV::LR_D; in getLRForRMW64() 225 return RISCV::SC_D; in getSCForRMW64() 227 return RISCV::SC_D; in getSCForRMW64() [all …]
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H A D | RISCVISelDAGToDAG.cpp | 243 RISCV::VRN2M1RegClassID, RISCV::VRN3M1RegClassID, RISCV::VRN4M1RegClassID, in createTuple() 244 RISCV::VRN5M1RegClassID, RISCV::VRN6M1RegClassID, RISCV::VRN7M1RegClassID, in createTuple() 453 const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo( in selectVLXSEG() 494 const RISCV::VSSEGPseudo *P = RISCV::getVSSEGPseudo( in selectVSSEG() 926 Opc = HasZdinx ? RISCV::COPY : RISCV::FMV_D_X; in Select() 2145 const RISCV::VLEPseudo *P = RISCV::getVLEPseudo( in Select() 3282 case RISCV::ADD: Opc = RISCV::ADDW; break; in doPeepholeSExtW() 3283 case RISCV::ADDI: Opc = RISCV::ADDIW; break; in doPeepholeSExtW() 3284 case RISCV::SUB: Opc = RISCV::SUBW; break; in doPeepholeSExtW() 3285 case RISCV::MUL: Opc = RISCV::MULW; break; in doPeepholeSExtW() [all …]
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H A D | RISCVFrameLowering.cpp | 46 RISCV::X1, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, 47 RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, 48 RISCV::X25, RISCV::X26, RISCV::X27}; 82 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW)) in emitSCSPrologue() 132 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW)) in emitSCSEpilogue() 427 if (Reg == RISCV::X2) in createDefCFAExpression() 999 RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */ in determineCalleeSaves() 1001 RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, in determineCalleeSaves() 1002 RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31 /* t3-t6 */ in determineCalleeSaves() 1015 for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++) in determineCalleeSaves() [all …]
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H A D | RISCVInsertVSETVLI.cpp | 88 case RISCV::VMV_X_S: in isScalarExtractInstr() 98 case RISCV::VMV_S_X: in isScalarInsertInstr() 108 case RISCV::VMV_V_I: in isScalarSplatInstr() 109 case RISCV::VMV_V_X: in isScalarSplatInstr() 133 case RISCV::VLE8_V: in getEEWForLoadStore() 134 case RISCV::VLSE8_V: in getEEWForLoadStore() 135 case RISCV::VSE8_V: in getEEWForLoadStore() 136 case RISCV::VSSE8_V: in getEEWForLoadStore() 138 case RISCV::VLE16_V: in getEEWForLoadStore() 140 case RISCV::VSE16_V: in getEEWForLoadStore() [all …]
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H A D | RISCVFoldMasks.cpp | 77 case RISCV::PseudoVMSET_M_B1: in isAllOnesMask() 78 case RISCV::PseudoVMSET_M_B2: in isAllOnesMask() 79 case RISCV::PseudoVMSET_M_B4: in isAllOnesMask() 80 case RISCV::PseudoVMSET_M_B8: in isAllOnesMask() 81 case RISCV::PseudoVMSET_M_B16: in isAllOnesMask() 82 case RISCV::PseudoVMSET_M_B32: in isAllOnesMask() 83 case RISCV::PseudoVMSET_M_B64: in isAllOnesMask() 137 const RISCV::RISCVMaskedPseudoInfo *I = in convertToUnmasked() 138 RISCV::getMaskedPseudoInfo(MI.getOpcode()); in convertToUnmasked() 171 if (MI.getOperand(PassthruOpIdx).getReg() != RISCV::NoRegister) in convertToUnmasked() [all …]
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H A D | RISCVRVVInitUndef.cpp | 99 return &RISCV::VRM8RegClass; in getVRLargestSuperClass() 101 return &RISCV::VRM4RegClass; in getVRLargestSuperClass() 103 return &RISCV::VRM2RegClass; in getVRLargestSuperClass() 105 return &RISCV::VRRegClass; in getVRLargestSuperClass() 119 case RISCV::VRRegClassID: in getUndefInitOpcode() 120 return RISCV::PseudoRVVInitUndefM1; in getUndefInitOpcode() 121 case RISCV::VRM2RegClassID: in getUndefInitOpcode() 122 return RISCV::PseudoRVVInitUndefM2; in getUndefInitOpcode() 123 case RISCV::VRM4RegClassID: in getUndefInitOpcode() 124 return RISCV::PseudoRVVInitUndefM4; in getUndefInitOpcode() [all …]
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H A D | RISCVMoveMerger.cpp | 64 if ((Destination == RISCV::X10 || Destination == RISCV::X11) && in isCandidateToMergeMVA01S() 65 RISCV::SR07RegClass.contains(Source)) in isCandidateToMergeMVA01S() 75 if ((Source == RISCV::X10 || Source == RISCV::X11) && in isCandidateToMergeMVSA01() 76 RISCV::SR07RegClass.contains(Destination)) in isCandidateToMergeMVSA01() 90 Register ARegInFirstPair = Opcode == RISCV::CM_MVA01S in mergePairedInsns() 106 bool StartWithX10 = ARegInFirstPair == RISCV::X10; in mergePairedInsns() 107 if (Opcode == RISCV::CM_MVA01S) { in mergePairedInsns() 142 if (InstOpcode == RISCV::CM_MVA01S && in findMatchingInst() 157 } else if (InstOpcode == RISCV::CM_MVSA01 && in findMatchingInst() 191 Opcode = RISCV::CM_MVA01S; in mergeMoveSARegPair() [all …]
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H A D | RISCVPushPopOptimizer.cpp | 52 if (MBBI->getOpcode() == RISCV::CM_POP) in containsPop() 64 unsigned Opc = IsReturnZero ? RISCV::CM_POPRETZ : RISCV::CM_POPRET; in usePopRet() 91 if (DestReg == RISCV::X10 && Source == RISCV::X0) { in adjustRetVal() 100 if (!ModifiedRegUnits.available(RISCV::X10) || in adjustRetVal() 101 !UsedRegUnits.available(RISCV::X10)) in adjustRetVal() 133 NextI->getOpcode() == RISCV::PseudoRET) in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
H A D | RISCVMCCodeEmitter.cpp | 128 Ra = RISCV::X6; in expandFunctionCall() 134 Ra = RISCV::X1; in expandFunctionCall() 225 return RISCV::BNE; in getInvertedBranchOp() 227 return RISCV::BEQ; in getInvertedBranchOp() 250 Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ; in expandLongCondBr() 255 if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 && in expandLongCondBr() 258 } else if (RISCV::X8 <= SrcReg2.id() && SrcReg2.id() <= RISCV::X15 && in expandLongCondBr() 268 Opcode == RISCV::PseudoLongBNE ? RISCV::C_BEQZ : RISCV::C_BNEZ; in expandLongCondBr() 284 MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol); in expandLongCondBr() 401 RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid; in getImmOpValue() [all …]
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H A D | RISCVMatInt.cpp | 24 case RISCV::SLLI: in getInstSeqCost() 25 case RISCV::SRLI: in getInstSeqCost() 28 case RISCV::ADDI: in getInstSeqCost() 29 case RISCV::ADDIW: in getInstSeqCost() 30 case RISCV::LUI: in getInstSeqCost() 74 unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; in generateInstSeqImpl() 147 unsigned Opc = Unsigned ? RISCV::SLLI_UW : RISCV::SLLI; in generateInstSeqImpl() 494 case RISCV::LUI: in getOpndKind() 501 case RISCV::PACK: in getOpndKind() 503 case RISCV::ADDI: in getOpndKind() [all …]
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H A D | RISCVELFObjectWriter.cpp | 74 case RISCV::fixup_riscv_got_hi20: in getRelocType() 88 case RISCV::fixup_riscv_jal: in getRelocType() 90 case RISCV::fixup_riscv_branch: in getRelocType() 92 case RISCV::fixup_riscv_rvc_jump: in getRelocType() 96 case RISCV::fixup_riscv_call: in getRelocType() 129 case RISCV::fixup_riscv_hi20: in getRelocType() 131 case RISCV::fixup_riscv_lo12_i: in getRelocType() 133 case RISCV::fixup_riscv_lo12_s: in getRelocType() 141 case RISCV::fixup_riscv_tprel_add: in getRelocType() 143 case RISCV::fixup_riscv_relax: in getRelocType() [all …]
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H A D | RISCVAsmBackend.cpp | 187 case RISCV::C_J: in relaxInstruction() 194 case RISCV::BEQ: in relaxInstruction() 195 case RISCV::BNE: in relaxInstruction() 196 case RISCV::BLT: in relaxInstruction() 197 case RISCV::BGE: in relaxInstruction() 198 case RISCV::BLTU: in relaxInstruction() 362 case RISCV::C_J: in getRelaxedOpcode() 365 case RISCV::BEQ: in getRelaxedOpcode() 367 case RISCV::BNE: in getRelaxedOpcode() 369 case RISCV::BLT: in getRelaxedOpcode() [all …]
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H A D | RISCVMCTargetDesc.cpp | 122 return Reg >= RISCV::X0 && Reg <= RISCV::X31; in isGPR() 232 case RISCV::JAL: in isTerminator() 233 case RISCV::JALR: in isTerminator() 245 case RISCV::JAL: in isCall() 246 case RISCV::JALR: in isCall() 258 case RISCV::JALR: in isReturn() 261 case RISCV::C_JR: in isReturn() 287 case RISCV::JALR: in isIndirectBranch() 290 case RISCV::C_JR: in isIndirectBranch() 298 return Reg == RISCV::X1 || Reg == RISCV::X5; in maybeReturnAddress() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/ |
H A D | RISCVCustomBehaviour.cpp | 192 case RISCV::VLM_V: in getEEWAndEMUL() 193 case RISCV::VSM_V: in getEEWAndEMUL() 229 return Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V || in opcodeHasEEWAndEMULInfo() 230 Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V || in opcodeHasEEWAndEMULInfo() 231 Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V || in opcodeHasEEWAndEMULInfo() 232 Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V || in opcodeHasEEWAndEMULInfo() 233 Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V || in opcodeHasEEWAndEMULInfo() 234 Opcode == RISCV::VLSE8_V || Opcode == RISCV::VSSE8_V || in opcodeHasEEWAndEMULInfo() 235 Opcode == RISCV::VLSE16_V || Opcode == RISCV::VSSE16_V || in opcodeHasEEWAndEMULInfo() 236 Opcode == RISCV::VLSE32_V || Opcode == RISCV::VSSE32_V || in opcodeHasEEWAndEMULInfo() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVRegisterBankInfo.cpp | 25 namespace RISCV { namespace 83 case RISCV::GPRRegClassID: in getRegBankFromRegClass() 91 case RISCV::GPRCRegClassID: in getRegBankFromRegClass() 93 case RISCV::SR07RegClassID: in getRegBankFromRegClass() 94 case RISCV::SPRegClassID: in getRegBankFromRegClass() 103 case RISCV::VMRegClassID: in getRegBankFromRegClass() 104 case RISCV::VRRegClassID: in getRegBankFromRegClass() 106 case RISCV::VRM2RegClassID: in getRegBankFromRegClass() 122 unsigned Idx = Size == 64 ? RISCV::FPRB64Idx : RISCV::FPRB32Idx; in getFPValueMapping() 240 &RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx in getInstrMapping() [all …]
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H A D | RISCVInstructionSelector.cpp | 207 unsigned NegOpc = Subtarget->is64Bit() ? RISCV::SUBW : RISCV::SUB; in selectShiftMask() 439 RHS = RISCV::X0; in getOperandsForBranch() 453 RHS = RISCV::X0; in getOperandsForBranch() 462 LHS = RISCV::X0; in getOperandsForBranch() 572 unsigned Opcode = Size == 64 ? RISCV::FMV_D_X : RISCV::FMV_W_X; in select() 638 auto ADD = MIB.buildInstr(RISCV::ADD, {&RISCV::GPRRegClass}, in select() 643 unsigned LdOpc = EntrySize == 8 ? RISCV::LD : RISCV::LW; in select() 657 Dest = MIB.buildInstr(RISCV::ADD, {&RISCV::GPRRegClass}, in select() 1128 return Size == 32 ? RISCV::FLT_S : RISCV::FLT_D; in getFCmpOpcode() 1130 return Size == 32 ? RISCV::FLE_S : RISCV::FLE_D; in getFCmpOpcode() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
H A D | RISCVDisassembler.cpp | 72 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRRegisterClass() 80 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRX1X5RegisterClass() 81 if (Reg != RISCV::X1 && Reg != RISCV::X5) in DecodeGPRX1X5RegisterClass() 169 MCRegister Reg = RISCV::X8 + RegNo; in DecodeGPRCRegisterClass() 180 MCRegister Reg = RISCV::X0 + RegNo; in DecodeGPRPairRegisterClass() 191 MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18); in DecodeSR07RegisterClass() 217 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass() 234 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass() 251 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass() 264 MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister; in decodeVMaskReg() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
H A D | RISCVAsmParser.cpp | 1265 return Reg - RISCV::F0_D + RISCV::F0_H; in convertFPR64ToFPR16() 1270 return Reg - RISCV::F0_D + RISCV::F0_F; in convertFPR64ToFPR32() 1637 assert(!(Reg >= RISCV::F0_H && Reg <= RISCV::F31_H)); in matchRegisterNameHelper() 1638 assert(!(Reg >= RISCV::F0_F && Reg <= RISCV::F31_F)); in matchRegisterNameHelper() 1644 if (IsRVE && Reg >= RISCV::X16 && Reg <= RISCV::X31) in matchRegisterNameHelper() 3166 unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadGlobalAddress() 3196 unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW; in emitLoadTLSIEAddress() 3247 unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; in emitPseudoExtend() 3398 if (Opcode == RISCV::TH_LDD || Opcode == RISCV::TH_LWUD || in validateInstruction() 3437 if (Opcode == RISCV::VC_V_XVW || Opcode == RISCV::VC_V_IVW || in validateInstruction() [all …]
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