/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrSSE.td | 402 VEX, WIG; 406 VEX, WIG; 410 VEX, WIG; 414 VEX, WIG; 701 VEX, WIG; 706 VEX, WIG; 4078 VEX, WIG; 4084 VEX, WIG; 4208 VEX; 5702 VEX, WIG; [all …]
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H A D | X86InstrAMX.td | 49 defm "" : AMX_TILE_COMMON<"", NoEGPR>, VEX; 55 "tilerelease", [(int_x86_tilerelease)]>, VEX, T8, PS; 58 VEX, T8, XD; 104 VEX, VVVV, T8, XD; 108 VEX, VVVV, T8, XS; 112 VEX, VVVV, T8, PD; 116 VEX, VVVV, T8; 176 []>, VEX, VVVV, T8, XS; 206 []>, VEX, VVVV, T8, XD; 235 []>, T8, PD, VEX, VVVV; [all …]
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H A D | X86InstrMisc.td | 1227 defm BLSR32 : Bls<"blsr", MRM1r, MRM1m, Xi32>, VEX; 1228 defm BLSR64 : Bls<"blsr", MRM1r, MRM1m, Xi64>, VEX; 1229 defm BLSMSK32 : Bls<"blsmsk", MRM2r, MRM2m, Xi32>, VEX; 1230 defm BLSMSK64 : Bls<"blsmsk", MRM2r, MRM2m, Xi64>, VEX; 1231 defm BLSI32 : Bls<"blsi", MRM3r, MRM3m, Xi32>, VEX; 1232 defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64>, VEX; 1391 defm PDEP32 : PdepPext<"pdep", Xi32, X86pdep>, XD, VEX; 1392 defm PDEP64 : PdepPext<"pdep", Xi64, X86pdep>, XD, REX_W, VEX; 1393 defm PEXT32 : PdepPext<"pext", Xi32, X86pext>, XS, VEX; 1674 VEX, VVVV, T8, PD, Sched<[WriteXCHG]>; [all …]
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H A D | X86CompressEVEX.cpp | 255 case X86II::VEX: in CompressEVEXImpl()
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H A D | X86InstrFMA3Info.cpp | 148 bool IsFMA3Encoding = ((TSFlags & X86II::EncodingMask) == X86II::VEX && in getFMA3Group()
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H A D | X86InstrPredicates.td | 11 // Intel x86 instructions have three separate encoding spaces: legacy, VEX, and 28 // Besides, some instructions in legacy space with map 2/3 and VEX space are
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H A D | X86InstrFormats.td | 195 // Force the instruction to use REX2/VEX/EVEX encoding. 250 bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field?
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H A D | X86InstrUtils.td | 43 class VEX { Encoding OpEnc = EncVEX; } 864 VEX, VVVV, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>; 868 VEX, VVVV, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>; 872 VEX, VVVV, FMASC, Requires<[HasFMA, NoAVX512]>; 878 VEX, VVVV, FMASC, Requires<[HasFMA4, NoVLX]>; 882 VEX, VVVV, FMASC, Requires<[HasFMA4, NoAVX512]>; 886 VEX, VVVV, FMASC, Requires<[HasFMA4]>; 905 // XOP 5 operand instruction (VEX encoding!) 909 VEX, VVVV, Requires<[HasXOP]>;
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H A D | X86InstrShiftRotate.td | 555 def ri : RorXri<t>, VEX; 556 def mi : RorXmi<t>, VEX; 586 def rr : ShiftXrr<m, t>, VEX; 587 def rm : ShiftXrm<m, t>, VEX;
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H A D | X86ReplaceableInstrs.def | 405 // Special table for changing EVEX logic instructions to VEX. 406 // TODO: Should we run EVEX->VEX earlier?
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H A D | X86InstrArithmetic.td | 1335 defm ANDN32 : AndN<Xi32, "">, VEX, Requires<[HasBMI, NoEGPR]>; 1336 defm ANDN64 : AndN<Xi64, "">, VEX, REX_W, Requires<[HasBMI, NoEGPR]>; 1371 (ins t.RegClass:$src), "mulx", mulx_args, []>, T8, XD, VEX, 1375 (ins t.MemOperand:$src), "mulx", mulx_args, []>, T8, XD, VEX,
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H A D | X86InstrSystem.td | 445 [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX; 453 [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
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H A D | X86InstrAVX512.td | 828 // smaller extract to enable EVEX->VEX. 861 // smaller extract to enable EVEX->VEX. 2651 VEX, TB, PD; 2660 VEX, TB; 2668 VEX, TB, PD, REX_W; 2670 VEX, TB, XD; 2672 VEX, TB, REX_W; 2674 VEX, TB, XD, REX_W; 2895 VEX, VVVV, VEX_L, Sched<[sched]>; 2951 sched>, VEX, TA, PD; [all …]
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H A D | X86RegisterInfo.td | 794 // Represents the lower 16 registers that have VEX/legacy encodable subregs.
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H A D | X86ISelDAGToDAG.cpp | 1677 if ((TSFlags & X86II::EncodingMask) != X86II::VEX && in PostprocessISelDAG()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | X86CompressEVEXTablesEmitter.cpp | 183 if (RI.Encoding == X86Local::VEX) in run()
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H A D | X86RecognizableInstr.h | 172 enum { VEX = 1, XOP = 2, EVEX = 3 }; enumerator
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H A D | X86RecognizableInstr.cpp | 295 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { in insnContext()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86EncodingOptimization.cpp | 38 if (!Desc.isCommutable() || (TSFlags & X86II::EncodingMask) != X86II::VEX || in optimizeInstFromVEX3ToVEX2()
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H A D | X86BaseInfo.h | 824 VEX = 1 << EncodingShift, enumerator
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H A D | X86MCTargetDesc.cpp | 542 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX; in clearsSuperRegisters()
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H A D | X86MCCodeEmitter.cpp | 981 case X86II::VEX: in emitVEXOpcodePrefix()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEInstrVec.td | 1450 // Section 8.16.4 - VEX (Vector Expand) 1451 defm VEX : RV1m<"vex", 0x9d, V64, VM>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 4014 (MCID.TSFlags & X86II::EncodingMask) != X86II::VEX) in checkTargetMatchPredicate()
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/freebsd/crypto/heimdal/lib/wind/ |
H A D | UnicodeData.txt | 9637 A0F2;YI SYLLABLE VEX;Lo;0;L;;;;;N;;;;;
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