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Searched refs:DstReg (Results 1 – 25 of 59) sorted by relevance

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/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DR600ExpandSpecialInstrs.cpp126 unsigned DstReg; in runOnMachineFunction() local
129 DstReg = MI.getOperand(Chan).getReg(); in runOnMachineFunction()
131 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W; in runOnMachineFunction()
155 unsigned DstReg; in runOnMachineFunction() local
160 DstReg = MI.getOperand(Chan-2).getReg(); in runOnMachineFunction()
183 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
202 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
206 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
272 unsigned DstReg = MI.getOperand( in runOnMachineFunction() local
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
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H A DR600InstrInfo.h242 unsigned DstReg,
249 unsigned DstReg) const;
253 unsigned DstReg,
258 unsigned DstReg, unsigned SrcReg) const override;
H A DSIFixSGPRCopies.cpp182 unsigned DstReg = Copy.getOperand(0).getReg(); in isVGPRToSGPRCopy() local
187 = TargetRegisterInfo::isVirtualRegister(DstReg) ? in isVGPRToSGPRCopy()
188 MRI.getRegClass(DstReg) : in isVGPRToSGPRCopy()
189 TRI->getRegClass(DstReg); in isVGPRToSGPRCopy()
H A DSIShrinkInstructions.cpp218 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
219 if (TargetRegisterInfo::isVirtualRegister(DstReg)) { in runOnMachineFunction()
235 if (DstReg != AMDGPU::VCC) in runOnMachineFunction()
H A DAMDGPUInstrInfo.h52 unsigned &DstReg, unsigned &SubIdx) const override;
188 unsigned DstReg, unsigned SrcReg) const = 0;
/minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp140 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
143 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
148 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
162 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
164 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
179 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
181 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
191 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
194 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
199 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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H A DHexagonExpandPredSpillCode.cpp134 int DstReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
135 assert(Hexagon::PredRegsRegClass.contains(DstReg) && in runOnMachineFunction()
158 DstReg).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
167 DstReg).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
173 DstReg).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DRegisterCoalescer.h33 unsigned DstReg; variable
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), in CoalescerPair()
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
100 unsigned getDstReg() const { return DstReg; } in getDstReg()
H A DTwoAddressInstructionPass.cpp133 void scanUses(unsigned DstReg);
343 DstReg = 0; in isCopyToReg()
424 unsigned SrcReg, DstReg; in isKilled() local
678 unsigned Reg = DstReg; in scanUses()
734 unsigned SrcReg, DstReg; in processCopy() local
746 scanUses(DstReg); in processCopy()
796 unsigned DstReg; in rescheduleMIBelowKill() local
983 unsigned DstReg; in rescheduleKillAboveMI() local
1323 if (SrcReg == DstReg) in collectTiedOperands()
1335 SrcMO.setReg(DstReg); in collectTiedOperands()
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H A DOptimizePHIs.cpp92 unsigned DstReg = MI->getOperand(0).getReg(); in IsSingleValuePHICycle() local
105 if (SrcReg == DstReg) in IsSingleValuePHICycle()
135 unsigned DstReg = MI->getOperand(0).getReg(); in IsDeadPHICycle() local
136 assert(TargetRegisterInfo::isVirtualRegister(DstReg) && in IsDeadPHICycle()
147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) { in IsDeadPHICycle()
H A DExpandPostRAPseudos.cpp87 unsigned DstReg = MI->getOperand(0).getReg(); in LowerSubregToReg() local
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
95 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && in LowerSubregToReg()
113 if (DstReg != InsReg) { in LowerSubregToReg()
128 CopyMI->addRegisterDefined(DstReg); in LowerSubregToReg()
H A DRegisterCoalescer.cpp274 SrcReg = DstReg = 0; in setRegisters()
357 DstReg = Dst; in setRegisters()
364 std::swap(SrcReg, DstReg); in flip()
395 return DstReg == Dst; in isCoalescable()
400 if (DstReg != Dst) in isCoalescable()
889 unsigned NewDstReg = DstReg; in reMaterializeTrivialDef()
942 MRI->setRegClass(DstReg, NewRC); in reMaterializeTrivialDef()
944 updateRegDefsUses(DstReg, DstReg, DstIdx); in reMaterializeTrivialDef()
1015 UseMO.setReg(DstReg); in reMaterializeTrivialDef()
1187 MO.substPhysReg(DstReg, *TRI); in updateRegDefsUses()
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H A DPeepholeOptimizer.cpp317 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
318 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
321 if (TargetRegisterInfo::isPhysicalRegister(DstReg) || in INITIALIZE_PASS_DEPENDENCY()
331 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
347 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg)) in INITIALIZE_PASS_DEPENDENCY()
425 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg)) in INITIALIZE_PASS_DEPENDENCY()
439 MRI->clearKillFlags(DstReg); in INITIALIZE_PASS_DEPENDENCY()
440 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
446 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
H A DEarlyIfConversion.cpp463 unsigned DstReg = PI.PHI->getOperand(0).getReg(); in replacePHIInstrs() local
464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); in replacePHIInstrs()
484 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst)); in rewritePHIOperands() local
485 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); in rewritePHIOperands()
493 PI.PHI->getOperand(i-2).setReg(DstReg); in rewritePHIOperands()
H A DMachineSink.cpp151 unsigned DstReg = MI->getOperand(0).getReg(); in INITIALIZE_PASS_DEPENDENCY() local
153 !TargetRegisterInfo::isVirtualRegister(DstReg) || in INITIALIZE_PASS_DEPENDENCY()
158 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
167 MRI->replaceRegWith(DstReg, SrcReg); in INITIALIZE_PASS_DEPENDENCY()
/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp111 .addReg(DstReg) in tryOrrMovk()
187 .addReg(DstReg, in tryToreplicateChunks()
189 .addReg(DstReg) in tryToreplicateChunks()
213 .addReg(DstReg) in tryToreplicateChunks()
361 .addReg(DstReg, in trySequenceOfOnes()
363 .addReg(DstReg) in trySequenceOfOnes()
379 .addReg(DstReg) in trySequenceOfOnes()
551 .addReg(DstReg, in expandMOVImm()
554 .addReg(DstReg) in expandMOVImm()
648 .addReg(DstReg); in expandMI()
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H A DAArch64ConditionalCompares.cpp180 bool isDeadDef(unsigned DstReg);
258 bool SSACCmpConv::isDeadDef(unsigned DstReg) { in isDeadDef() argument
260 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in isDeadDef()
262 if (!TargetRegisterInfo::isVirtualRegister(DstReg)) in isDeadDef()
266 return MRI->use_nodbg_empty(DstReg); in isDeadDef()
H A DAArch64InstrInfo.h53 unsigned &DstReg, unsigned &SubIdx) const override;
152 DebugLoc DL, unsigned DstReg,
/minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp143 unsigned DstReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
145 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) in eliminateFrameIndex()
146 .addReg(DstReg).addImm(-Offset); in eliminateFrameIndex()
148 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) in eliminateFrameIndex()
149 .addReg(DstReg).addImm(Offset); in eliminateFrameIndex()
H A DMSP430InstrFormats.td40 def DstReg : DestMode<0>;
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
106 : IForm8<opcode, DstReg, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>;
127 : IForm16<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
131 : IForm16<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
135 : IForm16<opcode, DstReg, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>;
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp480 unsigned DstReg = I->getOperand(0).getReg(); in expandPseudoMTLoHi() local
494 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
509 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()
515 unsigned DstReg = I->getOperand(0).getReg(); in expandExtractElementF64() local
548 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
554 unsigned DstReg = I->getOperand(0).getReg(); in expandBuildPairF64() local
583 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) in expandBuildPairF64()
599 .addReg(DstReg) in expandBuildPairF64()
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H A DMipsOptimizePICCall.cpp135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64; in setCallTargetReg() local
136 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg) in setCallTargetReg()
138 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp524 unsigned DstReg = 0; in ExpandLaneOp() local
528 DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandLaneOp()
658 unsigned DstReg = MI.getOperand(0).getReg(); in ExpandMOV32BitImm() local
674 .addReg(DstReg); in ExpandMOV32BitImm()
704 .addReg(DstReg); in ExpandMOV32BitImm()
953 unsigned DstReg = MI.getOperand(0).getReg(); in ExpandMI() local
963 .addReg(DstReg) in ExpandMI()
975 unsigned DstReg = MI.getOperand(0).getReg(); in ExpandMI() local
1013 .addReg(DstReg) in ExpandMI()
1047 .addReg(DstReg) in ExpandMI()
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/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h119 unsigned &SrcReg, unsigned &DstReg,
154 unsigned DstReg,
H A DPPCFrameLowering.cpp299 unsigned DstReg = MI->getOperand(0).getReg(); in HandleVRSaveUpdate() local
302 if (DstReg != SrcReg) in HandleVRSaveUpdate()
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
311 if (DstReg != SrcReg) in HandleVRSaveUpdate()
312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
320 if (DstReg != SrcReg) in HandleVRSaveUpdate()
321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
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