/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 379 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost() 387 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
|
H A D | PPCISelLowering.cpp | 447 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in PPCTargetLowering()
|
/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 255 INSERT_VECTOR_ELT, enumerator
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 155 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering() 156 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering() 157 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering() 158 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering() 164 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in R600TargetLowering() 584 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation() 970 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT() 1883 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
|
H A D | SIISelLowering.cpp | 191 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
|
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypesGeneric.cpp | 436 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT() 440 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
|
H A D | LegalizeVectorTypes.cpp | 59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult() 594 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult() 890 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT() 893 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT() 1709 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult() 1924 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, in WidenVecRes_BinaryCanTrap() 2382 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT() 2946 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
|
H A D | SelectionDAGDumper.cpp | 200 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; in getOperationName()
|
H A D | LegalizeIntegerTypes.cpp | 87 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerResult() 835 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerOperand() 2579 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; in ExpandIntegerOperand() 3121 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, in PromoteIntRes_INSERT_VECTOR_ELT()
|
H A D | DAGCombiner.cpp | 1341 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); in visit() 10433 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() in visitINSERT_VECTOR_ELT() 10439 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT, in visitINSERT_VECTOR_ELT() 10442 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()), in visitINSERT_VECTOR_ELT()
|
H A D | LegalizeDAG.cpp | 3251 case ISD::INSERT_VECTOR_ELT: in ExpandNode()
|
H A D | SelectionDAG.cpp | 3319 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) { in getNode()
|
H A D | SelectionDAGBuilder.cpp | 3095 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(), in visitInsertElement()
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 103 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON() 563 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in ARMTargetLowering() 3123 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments() 3125 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments() 5247 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops); in LowerBUILD_VECTOR() 5311 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR() 5808 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS() 5812 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS() 6449 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation() 8829 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, in PerformInsertEltCombine() [all …]
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 475 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in AArch64TargetLowering() 619 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom); in addTypeForNEON() 1938 case ISD::INSERT_VECTOR_ELT: in LowerOperation() 5263 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE() 5949 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR() 5996 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR() 6007 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); in LowerINSERT_VECTOR_ELT() 6032 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, in LowerINSERT_VECTOR_ELT() 7773 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore() 7786 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore() [all …]
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 831 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in resetOperationActions() 928 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); in resetOperationActions() 996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in resetOperationActions() 997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in resetOperationActions() 998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in resetOperationActions() 1363 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in resetOperationActions() 1485 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom); in resetOperationActions() 1538 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in resetOperationActions() 5810 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in LowerBuildVectorv8i16() 6319 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT)) in buildFromShuffleMostly() [all …]
|
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAIntType() 306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAFloatType() 1920 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN() 2388 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()
|
/minix/external/bsd/llvm/dist/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAG.td | 375 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 485 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
|
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1437 case InsertElement: return ISD::INSERT_VECTOR_ELT; in InstructionOpcodeToISD()
|