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Searched refs:Latency (Results 1 – 25 of 35) sorted by relevance

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/minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedA57WriteRes.td15 // Latency: #cyc
64 let Latency = 6;
69 let Latency = 7;
74 let Latency = 8;
78 let Latency = 9;
82 let Latency = 8;
86 let Latency = 6;
90 let Latency = 6;
94 let Latency = 6;
99 let Latency = 5;
[all …]
H A DAArch64SchedA53.td57 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
58 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
61 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
62 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 3; }
65 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
66 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
73 def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; }
81 def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
95 def : WriteRes<WriteAdr, []> { let Latency = 0; }
98 def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; }
[all …]
H A DAArch64SchedCyclone.td155 let Latency = 2;
163 let Latency = 2;
175 let Latency = 2;
191 let Latency = 4;
195 let Latency = 5;
206 let Latency = 10;
213 let Latency = 13;
223 let Latency = 4;
233 let Latency = 4;
267 let Latency = 4;
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H A DAArch64SchedA57.td94 def : WriteRes<WriteSys, []> { let Latency = 1; }
95 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
96 def : WriteRes<WriteHint, []> { let Latency = 1; }
98 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
365 def A57WriteIVMA : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
376 def A57WriteIVA : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
462 def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
463 def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; }
529 def A57WriteFPMA : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
/minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCScheduleE5500.td53 [5, 2, 2], // Latency = 1
58 [5, 2, 2], // Latency = 1
63 [6, 2, 2], // Latency = 1 or 2
80 [11], // Latency = 7, Repeat rate = 1
112 [5, 2, 2], // Latency = 1
136 [5, 2], // Latency = 1
140 [5, 2, 2], // Latency = 1
145 [5, 2], // Latency = 1
149 [5, 2, 2], // Latency = 1
165 [7, 2], // Latency = 3
[all …]
H A DPPCScheduleE500mc.td49 [4, 1, 1], // Latency = 1
54 [4, 1, 1], // Latency = 1
70 [11], // Latency = 8
107 [4, 1], // Latency = 1
116 [4, 1], // Latency = 1
128 [6, 1], // Latency = 3
132 [6, 1], // Latency = 3
136 [6, 1], // Latency = 3
141 [6, 1], // Latency = 3
147 [6, 1], // Latency = 3
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86ScheduleBtVer2.td114 let Latency = 6;
120 let Latency = 25;
124 let Latency = 41;
201 let Latency = 2;
205 let Latency = 7;
219 let Latency = 2;
223 let Latency = 7;
229 let Latency = 1;
233 let Latency = 6;
238 let Latency = 3;
[all …]
H A DX86ScheduleSLM.td93 let Latency = 25;
97 let Latency = 29;
114 let Latency = 5;
118 let Latency = 8;
123 let Latency = 34;
183 let Latency = 8;
187 let Latency = 8;
192 let Latency = 8;
196 let Latency = 8;
201 let Latency = 8;
[all …]
H A DX86SchedSandyBridge.td128 let Latency = 2;
132 let Latency = 6;
144 let Latency = 2;
148 let Latency = 6;
152 let Latency = 6;
156 let Latency = 6;
183 let Latency = 3;
187 let Latency = 3;
193 let Latency = 4;
197 let Latency = 4;
[all …]
H A DX86SchedHaswell.td119 let Latency = 25;
142 let Latency = 2;
146 let Latency = 6;
160 let Latency = 2;
164 let Latency = 6;
169 let Latency = 2;
173 let Latency = 6;
178 let Latency = 6;
182 let Latency = 6;
229 let Latency = 7;
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DTargetSchedule.cpp194 unsigned Latency = capLatency(WLEntry->Cycles); in computeOperandLatency() local
196 return Latency; in computeOperandLatency()
201 return Latency; in computeOperandLatency()
206 return Latency - Advance; in computeOperandLatency()
232 unsigned Latency = 0; in computeInstrLatency() local
240 Latency = std::max(Latency, capLatency(WLEntry->Cycles)); in computeInstrLatency()
242 return Latency; in computeInstrLatency()
245 assert(Latency && "No MI sched latency"); in computeInstrLatency()
261 unsigned Latency = 0; in computeInstrLatency() local
267 Latency = std::max(Latency, capLatency(WLEntry->Cycles)); in computeInstrLatency()
[all …]
H A DCriticalAntiDepBreaker.cpp443 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) in BreakAntiDependencies()
450 << (Max->getDepth() + Max->Latency) << "\n"); in BreakAntiDependencies()
/minix/external/bsd/llvm/dist/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp172 int Latency = 0; in getItineraryLatency() local
175 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx)); in getItineraryLatency()
177 return Latency; in getItineraryLatency()
205 int Latency = 0; in getLatency() local
211 Latency = std::max(Latency, WLEntry->Cycles); in getLatency()
214 return Latency; in getLatency()
221 int Latency = getLatency(DC, Inst); in emitLatency() local
224 if (Latency < 2) in emitLatency()
227 DC->CommentStream << "Latency: " << Latency << '\n'; in emitLatency()
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/ARM/
H A D2012-06-12-SchedMemLatency.ll10 ; CHECK: ch SU(3): Latency=1
14 ; CHECK: ch SU(2): Latency=1
20 ; CHECK: ch SU(3): Latency=1
24 ; CHECK: ch SU(2): Latency=1
/minix/external/bsd/llvm/dist/llvm/include/llvm/MC/
H A DMCInstrItineraries.h159 unsigned Latency = 0, StartCycle = 0; in getStageLatency() local
162 Latency = std::max(Latency, StartCycle + IS->getCycles()); in getStageLatency()
165 return Latency; in getStageLatency()
/minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h92 unsigned Latency; variable
111 Latency = 0; in SDep()
115 Latency = 1; in SDep()
120 : Dep(S, Order), Contents(), Latency(0) { in SDep()
139 return overlaps(Other) && Latency == Other.Latency;
151 return Latency; in getLatency()
156 Latency = Lat; in setLatency()
292 unsigned short Latency; // Node latency.
329 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
345 NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp92 SU->Latency = Old->Latency; in Clone()
493 unsigned OpLatency = isChain ? 1 : OpSU->Latency; in AddSchedEdges()
610 SU->Latency = 0; in computeLatency()
616 SU->Latency = 1; in computeLatency()
623 SU->Latency = HighLatencyCycles; in computeLatency()
625 SU->Latency = 1; in computeLatency()
631 SU->Latency = 0; in computeLatency()
634 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
658 Latency = (Latency > 1) ? Latency - 1 : 1; in computeOperandLatency()
660 if (Latency >= 0) in computeOperandLatency()
[all …]
H A DScheduleDAGVLIW.cpp245 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops! in listScheduleTopDown()
/minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleSwift.td1104 let Latency = 4;
1107 let Latency = 6;
1120 let Latency = 3;
1124 let Latency = 3;
1130 let Latency = 3;
1133 let Latency = 4;
1137 let Latency = 0;
1263 let Latency = 5;
1295 let Latency = 5;
1300 let Latency = 1;
[all …]
H A DARMScheduleA9.td1926 def A9WriteIssue : SchedWriteRes<[]> { let Latency = 0; }
1936 def : WriteRes<WriteALUsi, [A9UnitALU]> { let Latency = 2; }
1942 def A9WriteMHi : SchedWriteRes<[A9UnitMul]> { let Latency = 5;
1975 let Latency = 4;
1979 let Latency = 7;
1983 let Latency = 9;
1994 def A9WriteL : SchedWriteRes<[A9UnitLS]> { let Latency = 3; }
1996 def A9WriteLHi : SchedWriteRes<[]> { let Latency = 3;
2057 def A9WriteLMHi : SchedWriteRes<[]> { let Latency = 2;
2115 let Latency = 1;
[all …]
H A DARMBaseInstrInfo.cpp3671 --Latency; in getOperandLatency()
3688 if (Latency < 0) in getOperandLatency()
3700 return Latency; in getOperandLatency()
3721 return Latency <= 2 ? 1 : Latency - 1; in getOperandLatency()
3723 return Latency <= 3 ? 1 : Latency - 2; in getOperandLatency()
3750 --Latency; in getOperandLatency()
3761 --Latency; in getOperandLatency()
3780 --Latency; in getOperandLatency()
3913 ++Latency; in getOperandLatency()
3917 return Latency; in getOperandLatency()
[all …]
H A DARMSchedule.td19 // Uops | Latency from register | Uops - resource requirements - latency
49 // Latency = 4; // Latency of 4.
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/AArch64/
H A Darm64-misched-forwarding-A53.ll11 ; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2
12 ; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2
/minix/minix/drivers/power/acpi/include/
H A Dactbl3.h555 UINT32 Latency; member
575 UINT32 Latency; member
/minix/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DSISchedule.td48 let Latency = latency;

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