| /minix/external/bsd/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrInfo.h | 27 const MCInstrDesc *Desc; // Raw array to allow static init'n
35 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
48 const MCInstrDesc &get(unsigned Opcode) const { in get()
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| /minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 26 class MCInstrDesc; variable
236 const MCInstrDesc &MCID) { in BuildMI()
245 const MCInstrDesc &MCID, in BuildMI()
258 const MCInstrDesc &MCID, in BuildMI()
269 const MCInstrDesc &MCID, in BuildMI()
280 const MCInstrDesc &MCID, in BuildMI()
298 const MCInstrDesc &MCID) { in BuildMI()
308 const MCInstrDesc &MCID) { in BuildMI()
318 const MCInstrDesc &MCID) { in BuildMI()
334 const MCInstrDesc &MCID) { in BuildMI()
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| H A D | DFAPacketizer.h | 35 class MCInstrDesc; variable
68 bool canReserveResources(const llvm::MCInstrDesc *MID);
72 void reserveResources(const llvm::MCInstrDesc *MID);
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| H A D | MachineInstr.h | 71 const MCInstrDesc *MCID; // Instruction descriptor.
113 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
276 const MCInstrDesc &getDesc() const { return *MCID; }
1137 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
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| H A D | ScheduleDAG.h | 38 class MCInstrDesc; variable
584 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
616 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.h | 26 class MCInstrDesc; variable
53 const MCInstrDesc &II,
68 const MCInstrDesc *II,
79 const MCInstrDesc *II,
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| H A D | InstrEmitter.cpp | 132 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); in EmitCopyFromReg()
208 const MCInstrDesc &II, in CreateVirtualRegisters()
314 const MCInstrDesc *II, in AddRegisterOperand()
324 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
376 const MCInstrDesc *II, in AddOperand()
610 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
664 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValue()
745 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
852 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode()
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| H A D | FastISel.cpp | 1702 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_()
1711 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_r()
1733 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_rr()
1758 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_rrr()
1784 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_ri()
1807 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_rii()
1831 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_rf()
1854 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_rri()
1881 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_rrii()
1908 const MCInstrDesc &II = TII.get(MachineInstOpcode); in fastEmitInst_i()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
67 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother()
176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType()
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| H A D | PPCFrameLowering.cpp | 559 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 in emitPrologue()
561 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD in emitPrologue()
563 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU in emitPrologue()
565 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX in emitPrologue()
569 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 in emitPrologue()
571 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitPrologue()
910 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 in emitEpilogue()
912 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD in emitEpilogue()
916 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 in emitEpilogue()
918 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 in emitEpilogue()
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| H A D | PPCHazardRecognizers.h | 33 bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| H A D | ARMBaseInstrInfo.h | 301 const MCInstrDesc &DefMCID,
305 const MCInstrDesc &DefMCID,
309 const MCInstrDesc &UseMCID,
313 const MCInstrDesc &UseMCID,
317 const MCInstrDesc &DefMCID,
319 const MCInstrDesc &UseMCID,
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| H A D | MLxExpansionPass.cpp | 187 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
287 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
344 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
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| H A D | Thumb2SizeReduction.cpp | 213 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef()
548 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial()
683 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2); in ReduceTo2Addr()
697 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr()
761 const MCInstrDesc &MCID = MI->getDesc(); in ReduceToNarrow()
780 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1); in ReduceToNarrow()
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| H A D | ARMBaseInstrInfo.cpp | 156 const MCInstrDesc &MCID = MI->getDesc(); in convertToThreeAddress()
604 const MCInstrDesc &MCID = MI->getDesc(); in GetInstSizeInBytes()
1866 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
2104 const MCInstrDesc &Desc = MI.getDesc(); in rewriteARMFrameIndex()
2620 const MCInstrDesc &DefMCID = DefMI->getDesc(); in FoldImmediate()
2630 const MCInstrDesc &UseMCID = UseMI->getDesc(); in FoldImmediate()
2726 const MCInstrDesc &Desc = MI->getDesc(); in getNumMicroOpsSwiftLdSt()
2982 const MCInstrDesc &Desc = MI->getDesc(); in getNumMicroOps()
3623 const MCInstrDesc *DefMCID = &DefMI->getDesc(); in getOperandLatency()
3928 const MCInstrDesc &MCID = MI->getDesc(); in getPredicationCost()
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 66 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) { in canReserveResources()
78 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { in reserveResources()
92 const llvm::MCInstrDesc &MID = MI->getDesc(); in canReserveResources()
99 const llvm::MCInstrDesc &MID = MI->getDesc(); in reserveResources()
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| H A D | ScoreboardHazardRecognizer.cpp | 129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType()
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInst.h | 32 HexagonMCInst(const MCInstrDesc &mcid);
59 MCInstrDesc const &getDesc() const;
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| H A D | HexagonMCInst.cpp | 24 HexagonMCInst::HexagonMCInst(MCInstrDesc const &mcid) : MCInst() {} in HexagonMCInst()
80 MCInstrDesc const& HexagonMCInst::getDesc() const { return (MCII->get(getOpcode())); } in getDesc()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/R600/MCTargetDesc/ |
| H A D | SIMCCodeEmitter.cpp | 48 bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
86 bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc, in isSrcOperand()
144 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in EncodeInstruction()
232 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValue()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | Mips16InstrInfo.h | 101 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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| /minix/external/bsd/llvm/dist/llvm/lib/MC/MCDisassembler/ |
| H A D | Disassembler.cpp | 169 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode()); in getItineraryLatency()
196 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode()); in getLatency()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 413 const MCInstrDesc& TID = MI->getDesc(); in isCondInst()
552 const MCInstrDesc& MCID = PacketMI->getDesc(); in CanPromoteToNewValueStore()
768 const MCInstrDesc &desc = QII->get(NewOpcode); in CanPromoteToDotNew()
964 const MCInstrDesc& TID = MI->getDesc(); in ignorePseudoInstruction()
1000 const MCInstrDesc &MCIDI = I->getDesc(); in isLegalToPacketizeTogether()
1001 const MCInstrDesc &MCIDJ = J->getDesc(); in isLegalToPacketizeTogether()
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