| /minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 302 MULHU, MULHS, enumerator
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| H A D | SelectionDAG.h | 1069 case ISD::MULHS:
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelDAGToDAG.cpp | 179 case ISD::MULHS: { in Select()
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| H A D | SparcISelLowering.cpp | 1555 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 308 case ISD::MULHS: in selectNode()
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| H A D | MipsSEISelLowering.cpp | 116 setOperationAction(ISD::MULHS, MVT::i32, Custom); in MipsSETargetLowering()
127 setOperationAction(ISD::MULHS, MVT::i64, Custom); in MipsSETargetLowering()
161 setOperationAction(ISD::MULHS, MVT::i32, Legal); in MipsSETargetLowering()
208 setOperationAction(ISD::MULHS, MVT::i64, Legal); in MipsSETargetLowering()
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 207 X86_INTRINSIC_DATA(avx2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
438 X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
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| H A D | X86ISelLowering.cpp | 432 setOperationAction(ISD::MULHS, VT, Expand); in resetOperationActions()
850 setOperationAction(ISD::MULHS, VT, Expand); in resetOperationActions()
908 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); in resetOperationActions()
909 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); in resetOperationActions()
910 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); in resetOperationActions()
911 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); in resetOperationActions()
975 setOperationAction(ISD::MULHS, MVT::v8i16, Legal); in resetOperationActions()
1301 setOperationAction(ISD::MULHS, MVT::v16i16, Legal); in resetOperationActions()
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 168 case ISD::MULHS: return "mulhs"; in getOperationName()
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| H A D | TargetLowering.cpp | 2680 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : in BuildSDIV()
2681 isOperationLegalOrCustom(ISD::MULHS, VT)) in BuildSDIV()
2682 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), in BuildSDIV()
2804 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT); in expandMUL()
2857 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL); in expandMUL()
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| H A D | LegalizeDAG.cpp | 3645 case ISD::MULHS: { in ExpandNode()
3672 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); in ExpandNode()
3776 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; in ExpandNode()
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| H A D | LegalizeVectorTypes.cpp | 1728 case ISD::MULHS: in WidenVectorResult()
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| H A D | DAGCombiner.cpp | 1284 case ISD::MULHS: return visitMULHS(N); in visit()
2414 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); in visitSMUL_LOHI()
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| H A D | SelectionDAG.cpp | 3141 case ISD::MULHS: in getNode()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 143 setOperationAction(ISD::MULHS, MVT::i8, Expand); in MSP430TargetLowering()
148 setOperationAction(ISD::MULHS, MVT::i16, Expand); in MSP430TargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 105 setOperationAction(ISD::MULHS, MVT::i32, Expand); in XCoreTargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 332 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | AMDGPUISelLowering.cpp | 286 setOperationAction(ISD::MULHS, MVT::i64, Expand); in AMDGPUTargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 174 setOperationAction(ISD::MULHS, VT, Expand); in SystemZTargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 557 setOperationAction(ISD::MULHS, VT, Expand); in AArch64TargetLowering()
1319 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
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| H A D | AArch64FastISel.cpp | 3593 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 415 setOperationAction(ISD::MULHS, VT, Expand); in ARMTargetLowering()
666 setOperationAction(ISD::MULHS, MVT::i32, Expand); in ARMTargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 450 setOperationAction(ISD::MULHS, VT, Expand); in PPCTargetLowering()
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