| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 884 if (MemOps[i].Position > MemOps[insertAfter].Position) { in MergeLDR_STR()
886 Loc = MemOps[i].MBBI; in MergeLDR_STR()
891 MergeOpsUpdate(MBB, MemOps, SIndex, MemOps.size(), insertAfter, SOffset, in MergeLDR_STR()
1424 Loc = MemOps[i].MBBI; in AdvanceRS()
1581 MemOpQueue MemOps; in LoadStoreMultipleOpti() local
1630 for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end(); I != E; ++I) { in LoadStoreMultipleOpti()
1662 for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end(); in LoadStoreMultipleOpti()
1699 AdvanceRS(MBB, MemOps); in LoadStoreMultipleOpti()
1723 if (!MemOps[i].Merged) in LoadStoreMultipleOpti()
1744 MemOps.clear(); in LoadStoreMultipleOpti()
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| H A D | ARMISelLowering.cpp | 2956 SmallVector<SDValue, 4> MemOps; in StoreByValRegs() local
2971 MemOps.push_back(Store); in StoreByValRegs()
2978 if (!MemOps.empty()) in StoreByValRegs()
2979 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in StoreByValRegs()
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| /minix/external/bsd/llvm/dist/llvm/test/CodeGen/Hexagon/ |
| H A D | memops2.ll | 2 ; Generate MemOps for V4 and above.
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| H A D | memops3.ll | 2 ; Generate MemOps for V4 and above.
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| H A D | memops1.ll | 2 ; Generate MemOps for V4 and above.
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| H A D | memops.ll | 2 ; Generate MemOps for V4 and above.
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 3894 MemOps.push_back(VT); in FindOptimalMemOpLowering()
3917 std::vector<EVT> MemOps; in getMemcpyLoadsAndStores() local
3965 EVT VT = MemOps[i]; in getMemcpyLoadsAndStores()
4032 std::vector<EVT> MemOps; in getMemmoveLoadsAndStores() local
4068 EVT VT = MemOps[i]; in getMemmoveLoadsAndStores()
4083 EVT VT = MemOps[i]; in getMemmoveLoadsAndStores()
4127 std::vector<EVT> MemOps; in getMemsetStores() local
4159 EVT LargestVT = MemOps[0]; in getMemsetStores()
4161 if (MemOps[i].bitsGT(LargestVT)) in getMemsetStores()
4162 LargestVT = MemOps[i]; in getMemsetStores()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1317 SmallVector<SDValue, 4> MemOps; in LowerCCCArguments() local
1398 MemOps.push_back(Store); in LowerCCCArguments()
1426 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, in LowerCCCArguments()
1437 if (!MemOps.empty()) { in LowerCCCArguments()
1438 MemOps.push_back(Chain); in LowerCCCArguments()
1439 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerCCCArguments()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 2516 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments_32SVR4() local
2563 MemOps.push_back(Store); in LowerFormalArguments_32SVR4()
2582 MemOps.push_back(Store); in LowerFormalArguments_32SVR4()
2590 if (!MemOps.empty()) in LowerFormalArguments_32SVR4()
2680 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments_64SVR4() local
2799 MemOps.push_back(Store); in LowerFormalArguments_64SVR4()
2941 MemOps.push_back(Store); in LowerFormalArguments_64SVR4()
2948 if (!MemOps.empty()) in LowerFormalArguments_64SVR4()
3059 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments_Darwin() local
3311 MemOps.push_back(Store); in LowerFormalArguments_Darwin()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 857 SmallVector<SDValue, 4> MemOps; in LowerFormalArguments() local
921 if (!MemOps.empty()) in LowerFormalArguments()
922 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments()
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| H A D | HexagonInstrInfoV4.td | 2653 // Define 'def Pats' for MemOps with register addend.
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 765 SDValue MemOps[SystemZ::NumArgFPRs]; in LowerFormalArguments() local
773 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN, in LowerFormalArguments()
780 makeArrayRef(&MemOps[NumFixedFPRs], in LowerFormalArguments()
1972 SDValue MemOps[NumFields]; in lowerVASTART() local
1979 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr, in lowerVASTART()
1984 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in lowerVASTART()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2216 SmallVector<SDValue, 8> MemOps; in saveVarArgRegisters() local
2238 MemOps.push_back(Store); in saveVarArgRegisters()
2268 MemOps.push_back(Store); in saveVarArgRegisters()
2277 if (!MemOps.empty()) { in saveVarArgRegisters()
2278 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in saveVarArgRegisters()
3881 SmallVector<SDValue, 4> MemOps; in LowerAAPCS_VASTART() local
3886 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList, in LowerAAPCS_VASTART()
3901 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr, in LowerAAPCS_VASTART()
3916 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr, in LowerAAPCS_VASTART()
3923 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32), in LowerAAPCS_VASTART()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2622 SmallVector<SDValue, 8> MemOps; in LowerFormalArguments() local
2634 MemOps.push_back(Store); in LowerFormalArguments()
2649 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, in LowerFormalArguments()
2653 if (!MemOps.empty()) in LowerFormalArguments()
2654 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments()
16676 SmallVector<SDValue, 8> MemOps; in LowerVASTART() local
16683 MemOps.push_back(Store); in LowerVASTART()
16692 MemOps.push_back(Store); in LowerVASTART()
16702 MemOps.push_back(Store); in LowerVASTART()
16711 MemOps.push_back(Store); in LowerVASTART()
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