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Searched refs:SP (Results 1 – 25 of 231) sorted by relevance

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/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp67 SP::G0, SP::G1, SP::G2, SP::G3,
68 SP::G4, SP::G5, SP::G6, SP::G7,
69 SP::O0, SP::O1, SP::O2, SP::O3,
70 SP::O4, SP::O5, SP::O6, SP::O7,
71 SP::L0, SP::L1, SP::L2, SP::L3,
72 SP::L4, SP::L5, SP::L6, SP::L7,
73 SP::I0, SP::I1, SP::I2, SP::I3,
74 SP::I4, SP::I5, SP::I6, SP::I7 };
77 SP::F0, SP::F1, SP::F2, SP::F3,
78 SP::F4, SP::F5, SP::F6, SP::F7,
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/InstPrinter/
H A DSparcInstPrinter.cpp29 using namespace SP;
58 case SP::JMPLrr: in printSparcAliasInstr()
82 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: in printSparcAliasInstr()
83 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { in printSparcAliasInstr()
155 case SP::FBCOND: in printCCOperand()
157 case SP::BPFCC: in printCCOperand()
161 case SP::MOVFCCrr: case SP::V9MOVFCCrr: in printCCOperand()
162 case SP::MOVFCCri: case SP::V9MOVFCCri: in printCCOperand()
163 case SP::FMOVS_FCC: case SP::V9FMOVS_FCC: in printCCOperand()
164 case SP::FMOVD_FCC: case SP::V9FMOVD_FCC: in printCCOperand()
[all …]
/minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp59 Reserved.set(SP::G1); in getReservedRegs()
71 Reserved.set(SP::O6); in getReservedRegs()
72 Reserved.set(SP::I6); in getReservedRegs()
73 Reserved.set(SP::I7); in getReservedRegs()
92 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
120 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) in replaceFI()
125 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) in replaceFI()
138 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) in replaceFI()
140 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1) in replaceFI()
143 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) in replaceFI()
[all …]
H A DSparcFrameLowering.cpp64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
69 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
82 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
161 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) in emitEpilogue()
194 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) in verifyLeafProcRegUse()
198 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg) in verifyLeafProcRegUse()
225 unsigned mapped_reg = (reg - SP::I0 + SP::O0); in remapRegsForLeafProc()
[all …]
H A DDelaySlotFiller.cpp285 case SP::CALLrr: in insertCallDefsUses()
286 case SP::CALLri: in insertCallDefsUses()
349 case SP::CALLrr: in needsUnimp()
371 if (reg < SP::I0 || reg > SP::I7) in combineRestoreADD()
383 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
399 if (reg < SP::I0 || reg > SP::I7) in combineRestoreOR()
422 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
437 if (reg < SP::I0 || reg > SP::I7) in combineRestoreSETHIi()
456 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
490 case SP::ADDrr: in tryCombineRestoreWithPrevInst()
[all …]
H A DSparcInstrInfo.cpp36 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), in SparcInstrInfo()
179 if (Opcode != SP::BCOND && Opcode != SP::FBCOND) in AnalyzeBranch()
269 if (I->getOpcode() != SP::BA in RemoveBranch()
289 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; in copyPhysReg()
290 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 }; in copyPhysReg()
291 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd, in copyPhysReg()
296 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
309 movOpc = SP::FMOVS; in copyPhysReg()
320 movOpc = SP::FMOVD; in copyPhysReg()
326 movOpc = SP::FMOVS; in copyPhysReg()
[all …]
H A DSparcAsmPrinter.cpp115 CallInst.setOpcode(SP::CALL); in EmitCall()
125 SETHIInst.setOpcode(SP::SETHIi); in EmitSETHI()
182 assert(MO.getReg() != SP::O7 && in LowerGETPCXAndEmitMCInsts()
266 case SP::GETPCX: in EmitInstruction()
284 const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 }; in EmitFunctionBodyStart()
290 if (reg == SP::G6 || reg == SP::G7) in EmitFunctionBodyStart()
306 if (MI->getOpcode() == SP::CALL) in printOperand()
309 else if (MI->getOpcode() == SP::SETHIi || MI->getOpcode() == SP::SETHIXi) in printOperand()
319 else if (MI->getOpcode() == SP::TLS_CALL) in printOperand()
330 else if (MI->getOpcode() == SP::TLS_LDrr) in printOperand()
[all …]
H A DSparcISelDAGToDAG.cpp137 R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy()); in SelectADDRrr()
165 TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS, in Select()
168 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); in Select()
170 TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart, in Select()
171 CurDAG->getRegister(SP::G0, MVT::i32)), 0); in Select()
174 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; in Select()
183 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; in Select()
187 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1)); in Select()
H A DSparcISelLowering.cpp57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in CC_Sparc_Assign_f64()
164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); in toCallerWindow()
165 if (Reg >= SP::I0 && Reg <= SP::I7) in toCallerWindow()
166 return Reg - SP::I0 + SP::O0; in toCallerWindow()
498 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 in LowerFormalArguments_32()
637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); in LowerFormalArguments_64()
1023 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; in fixupVariableFloatArgs()
2999 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in expandAtomicRMW()
3002 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg) in expandAtomicRMW()
3051 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg) in expandAtomicRMW()
[all …]
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/Mips/cconv/
H A Darguments-varargs.ll28 ; O32-DAG: sw $7, 20([[SP]])
29 ; O32-DAG: sw $6, 16([[SP]])
30 ; O32-DAG: sw $5, 12([[SP]])
32 ; NEW-DAG: sd $11, 56([[SP]])
33 ; NEW-DAG: sd $10, 48([[SP]])
34 ; NEW-DAG: sd $9, 40([[SP]])
35 ; NEW-DAG: sd $8, 32([[SP]])
36 ; NEW-DAG: sd $7, 24([[SP]])
37 ; NEW-DAG: sd $6, 16([[SP]])
38 ; NEW-DAG: sd $5, 8([[SP]])
[all …]
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/ARM/
H A D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll8 define void @foo(double %vfp0, ; --> D0, NSAA=SP
9 double %vfp1, ; --> D1, NSAA=SP
10 double %vfp2, ; --> D2, NSAA=SP
11 double %vfp3, ; --> D3, NSAA=SP
12 double %vfp4, ; --> D4, NSAA=SP
13 double %vfp5, ; --> D5, NSAA=SP
14 double %vfp6, ; --> D6, NSAA=SP
15 double %vfp7, ; --> D7, NSAA=SP
16 double %vfp8, ; --> SP, NSAA=SP+8 (!)
18 %st_t* byval %p1, ; --> SP+8, 4 words NSAA=SP+24
[all …]
H A D2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll10 define void @foo(double %vfp0, ; --> D0, NSAA=SP
12 double %vfp2, ; --> D2, NSAA=SP
13 double %vfp3, ; --> D3, NSAA=SP
14 double %vfp4, ; --> D4, NSAA=SP
15 double %vfp5, ; --> D5, NSAA=SP
16 double %vfp6, ; --> D6, NSAA=SP
17 double %vfp7, ; --> D7, NSAA=SP
18 double %vfp8, ; --> SP, NSAA=SP+8 (!)
20 %st_t* byval %p1, ; --> R1, R2, NSAA=SP+8
21 i32 %p2, ; --> R3, NSAA=SP+8
[all …]
/minix/external/bsd/llvm/dist/llvm/test/MC/ARM/
H A Darm-load-store-multiple-deprecated.s14 @ CHECK: warning: use of SP or PC in the list is deprecated
18 @ CHECK: warning: use of SP or PC in the list is deprecated
22 @ CHECK: warning: use of SP or PC in the list is deprecated
155 @ CHECK: warning: use of SP in the list is deprecated
157 @ CHECK: warning: use of SP in the list is deprecated
167 @ CHECK: warning: use of SP in the list is deprecated
169 @ CHECK: warning: use of SP in the list is deprecated
179 @ CHECK: warning: use of SP in the list is deprecated
181 @ CHECK: warning: use of SP in the list is deprecated
191 @ CHECK: warning: use of SP in the list is deprecated
[all …]
H A Dthumb2-strd.s8 strd r12, SP, [r0, #256]
9 strd r12, SP, [r0, #256]!
10 strd r12, SP, [r0], #256
H A Dthumb-load-store-multiple.s15 @ CHECK: error: SP may not be in the register list
33 @ CHECK: error: SP may not be in the register list
47 @ CHECK: error: SP may not be in the register list
51 @ CHECK: error: SP and PC may not be in the register list
57 @ CHECK: error: SP may not be in the register list
61 @ CHECK: error: SP and PC may not be in the register list
67 @ CHECK: error: SP may not be in the register list
71 @ CHECK: error: SP and PC may not be in the register list
77 @ CHECK-V7M: error: SP may not be in the register list
/minix/libexec/ftpd/
H A Dftpcmd.y137 SP CRLF COMMA ALL
446 | ALLO check_login SP NUMBER SP R SP NUMBER CRLF
546 | SITE SP CHMOD SP octal_number SP pathname CRLF
561 | SITE SP HELP SP STRING CRLF
578 | SITE SP IDLE check_login SP NUMBER CRLF
606 | SITE SP RATEGET check_login SP STRING CRLF
638 | SITE SP RATEPUT check_login SP STRING CRLF
672 | SITE SP UMASK check_login SP octal_number CRLF
1547 return (SP);
1582 return (SP);
[all …]
/minix/crypto/external/bsd/heimdal/dist/cf/
H A Dw32-def-from-dll.pl47 open(SP, '-|', "dumpbin /exports \"".$fn."\"") or die "Can't open pipe for $fn";
50 while (<SP>) {
61 close SP;
73 open(SP, '-|', "dumpbin /exports \"".$fn."\"") or die "Can't open pipe for $fn";
76 while (<SP>) {
116 close SP;
125 open(SP, '-|', "dumpbin /symbols \"".$fn."\"") or die "Can't open pipe for $fn";
128 while (<SP>) {
150 close SP;
/minix/external/bsd/llvm/dist/llvm/tools/opt/
H A DBreakpointPrinter.cpp58 DISubprogram SP(NMD->getOperand(i)); in runOnModule() local
59 assert((!SP || SP.isSubprogram()) && in runOnModule()
61 if (!SP) in runOnModule()
63 getContextName(SP.getContext().resolve(TypeIdentifierMap), Name); in runOnModule()
64 Name = Name + SP.getDisplayName().str(); in runOnModule()
/minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp72 .addReg(MSP430::SP); in emitPrologue()
99 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
100 .addReg(MSP430::SP).addImm(NumBytes); in emitPrologue()
162 TII.get(MSP430::SUB16ri), MSP430::SP) in emitEpilogue()
163 .addReg(MSP430::SP).addImm(CSSize); in emitEpilogue()
172 .addReg(MSP430::SP).addImm(NumBytes); in emitEpilogue()
249 TII.get(MSP430::SUB16ri), MSP430::SP) in eliminateCallFramePseudoInstr()
250 .addReg(MSP430::SP).addImm(Amount); in eliminateCallFramePseudoInstr()
258 TII.get(MSP430::ADD16ri), MSP430::SP) in eliminateCallFramePseudoInstr()
259 .addReg(MSP430::SP).addImm(Amount); in eliminateCallFramePseudoInstr()
[all …]
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/Thumb2/
H A Dfloat-cmp.ll152 ; SP: bl __aeabi_dcmpeq
161 ; SP: bl __aeabi_dcmpgt
170 ; SP: bl __aeabi_dcmpge
179 ; SP: bl __aeabi_dcmplt
188 ; SP: bl __aeabi_dcmple
198 ; SP: bl __aeabi_dcmpgt
199 ; SP: bl __aeabi_dcmplt
209 ; SP: bl __aeabi_dcmpun
219 ; SP: bl __aeabi_dcmpgt
220 ; SP: bl __aeabi_dcmpun
[all …]
H A Dfloat-ops.ll19 ; SP: bl __aeabi_dadd
38 ; SP: bl __aeabi_dsub
57 ; SP: bl __aeabi_dmul
76 ; SP: bl __aeabi_ddiv
141 ; SP: bl __aeabi_f2d
150 ; SP: bl __aeabi_d2f
168 ; SP: vmov r0, r1, d0
169 ; SP: bl __aeabi_d2iz
188 ; SP: vmov r0, r1, d0
207 ; SP: bl __aeabi_i2d
[all …]
/minix/crypto/external/bsd/openssl/dist/apps/demoCA/
H A Dindex.txt24 V 961206150305Z 010C unknown /C=AU/SP=QLD/O=Mincom Pty. Ltd./OU=MTR/CN=Eric Young/Email=eay@mincom…
25 V 961206153245Z 010D unknown /C=AU/SP=Queensland/O=Mincom Pty Ltd/OU=MTR/CN=Eric Young/Email=eay@m…
29 V 970324092238Z 0111 unknown /C=AU/SP=Queensland/CN=Eric Young
32 V 971001005237Z 0114 unknown /C=AU/SP=QLD/O=Mincom Pty Ltd/OU=MTR/CN=x509v3 test
33 V 971001010331Z 0115 unknown /C=AU/SP=Queensland/O=Mincom Pty Ltd/OU=MTR/CN=test again - x509v3
34 V 971001013945Z 0117 unknown /C=AU/SP=Queensland/O=Mincom Pty Ltd/OU=MTR/CN=x509v3 test
35 V 971014225415Z 0118 unknown /C=AU/SP=Queensland/CN=test
36 V 971015004448Z 0119 unknown /C=AU/SP=Queensland/O=Mincom Pty Ltd/OU=MTR/CN=test2
37 V 971016035001Z 011A unknown /C=AU/SP=Queensland/O=Mincom Pty Ltd/OU=MTR/CN=test64
/minix/external/bsd/llvm/dist/llvm/test/CodeGen/NVPTX/
H A Dlocal-stack-frame.ll7 ; PTX32: cvta.local.u32 %SP, %r{{[0-9]+}};
9 ; PTX32: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
11 ; PTX64: cvta.local.u64 %SP, %rd{{[0-9]+}};
13 ; PTX64: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
/minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h70 void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
74 void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
79 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
115 void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
120 void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
/minix/external/bsd/llvm/dist/llvm/lib/Transforms/Instrumentation/
H A DGCOVProfiling.cpp157 if (!SP.getLinkageName().empty()) in getFunctionName()
158 return SP.getLinkageName(); in getFunctionName()
159 return SP.getName(); in getFunctionName()
318 : SP(SP), Ident(Ident), UseCfgChecksum(UseCfgChecksum), CfgChecksum(0), in GCOVFunction()
337 FNLOS << getFunctionName(SP) << SP.getLineNumber(); in GCOVFunction()
383 write(SP.getLineNumber()); in writeOut()
418 DISubprogram SP; member in __anon67b605550211::GCOVFunction
502 assert((!SP || SP.isSubprogram()) && in emitProfileNotes()
504 if (!SP) in emitProfileNotes()
586 assert((!SP || SP.isSubprogram()) && in emitProfileArcs()
[all …]

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