| /minix/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 195 SDIVREM, UDIVREM, enumerator
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | R600ISelLowering.cpp | 878 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults() local
880 Results.push_back(UDIVREM); in ReplaceNodeResults()
887 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), in ReplaceNodeResults() local
889 Results.push_back(UDIVREM.getValue(1)); in ReplaceNodeResults()
917 case ISD::UDIVREM: { in ReplaceNodeResults()
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| H A D | AMDGPUISelLowering.cpp | 262 setOperationAction(ISD::UDIVREM, VT, Custom); in AMDGPUTargetLowering()
328 setOperationAction(ISD::UDIVREM, VT, Custom); in AMDGPUTargetLowering()
597 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
1852 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM()
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| /minix/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 176 case ISD::UDIVREM: return "udivrem"; in getOperationName()
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| H A D | LegalizeDAG.cpp | 2197 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in useDivRem()
3592 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3623 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3658 case ISD::UDIVREM: in ExpandNode()
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| H A D | DAGCombiner.cpp | 1290 case ISD::UDIVREM: return visitUDIVREM(N); in visit()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 130 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
137 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
214 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
371 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, in LowerOperation()
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| H A D | MipsISelLowering.cpp | 386 setTargetDAGCombine(ISD::UDIVREM); in MipsTargetLowering()
778 case ISD::UDIVREM: in PerformDAGCombine()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 154 setOperationAction(ISD::UDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
160 setOperationAction(ISD::UDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1326 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in HexagonTargetLowering()
1329 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in HexagonTargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1410 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1417 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 155 setOperationAction(ISD::UDIVREM, VT, Custom); in SystemZTargetLowering()
2436 case ISD::UDIVREM: in LowerOperation()
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| /minix/external/bsd/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 341 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2425 case ISD::UDIVREM: in Select()
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| H A D | X86ISelLowering.cpp | 854 setOperationAction(ISD::UDIVREM, VT, Expand); in resetOperationActions()
1664 setOperationAction(ISD::UDIVREM, MVT::i128, Custom); in resetOperationActions()
18300 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break; in LowerWin64_i128OP()
19744 case ISD::UDIVREM: { in ReplaceNodeResults()
25511 if (N0.getOpcode() == ISD::UDIVREM && in PerformZExtCombine()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 730 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in ARMTargetLowering()
733 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in ARMTargetLowering()
6469 case ISD::UDIVREM: return LowerDivRem(Op, DAG); in LowerOperation()
10768 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 152 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in PPCTargetLowering()
154 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in PPCTargetLowering()
453 setOperationAction(ISD::UDIVREM, VT, Expand); in PPCTargetLowering()
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| /minix/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 257 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in AArch64TargetLowering()
258 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in AArch64TargetLowering()
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