| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 122 case ISD::ADDE: in isdToLanaiAluCode()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 272 ADDE, enumerator
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| H A D | TargetLowering.h | 2437 case ISD::ADDE: in isCommutativeBinOp()
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| /netbsd/sys/external/bsd/sljit/dist/sljit_src/ |
| H A D | sljitNativePPC_32.c | 124 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)); in emit_single_op()
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| H A D | sljitNativePPC_64.c | 246 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)); in emit_single_op()
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| H A D | sljitNativePPC_common.c | 140 #define ADDE (HI(31) | LO(138)) macro
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 220 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!"); in selectAddE()
764 case ISD::ADDE: { in trySelect()
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| H A D | MipsSEISelLowering.cpp | 110 setOperationAction(ISD::ADDE, MVT::i32, Legal); in MipsSETargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1558 setOperationAction(ISD::ADDE, MVT::i32, Custom); in SparcTargetLowering()
1564 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
2911 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2912 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
3060 case ISD::ADDE: in LowerOperation()
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| H A D | SparcInstrInfo.td | 734 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 108 ADDE, // Add using carry enumerator
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| H A D | ARMISelLowering.cpp | 1653 MAKE_CASE(ARMISD::ADDE) in getTargetNodeName()
4787 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32), in ConvertCarryFlagToBooleanCarry()
9257 Result = DAG.getNode(ARMISD::ADDE, DL, VTs, Op.getOperand(0), in LowerADDSUBCARRY()
12187 assert((AddeSubeNode->getOpcode() == ARMISD::ADDE || in AddCombineTo64bitMLAL()
12197 if ((AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
12216 if (AddeSubeNode->getOpcode() == ARMISD::ADDE && in AddCombineTo64bitMLAL()
12395 (AddeNode->getOpcode() == ARMISD::ADDE) && in PerformUMLALCombine()
12416 if (LHS->getOpcode() == ARMISD::ADDE && in PerformAddcSubcCombine()
16955 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget); in PerformDAGCombine()
18091 case ARMISD::ADDE: in computeKnownBitsForTargetNode()
[all …]
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 298 case ISD::ADDE: return "adde"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 159 case ISD::ADDE: in PromoteIntegerResult()
2160 case ISD::ADDE: in ExpandIntegerResult()
2595 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
2692 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps); in ExpandIntRes_ADDSUBC()
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| H A D | TargetLowering.cpp | 6395 isOperationLegalOrCustom(ISD::ADDE, VT)); in expandMUL_LOHI()
6411 Hi = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(HiLoVT, MVT::Glue), Hi, Zero, in expandMUL_LOHI()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 107 setOperationAction(ISD::ADDE, VT, Custom); in M68kTargetLowering()
1336 case ISD::ADDE: in LowerOperation()
2462 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 728 case ISD::ADDE: in Select()
1017 bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE); in SelectADD_SUB_I64()
1020 bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE; in SelectADD_SUB_I64()
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| H A D | R600ISelLowering.cpp | 234 setOperationAction(ISD::ADDE, VT, Expand); in R600TargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 790 setOperationAction(ISD::ADDE, VT, Expand); in initActions()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 71 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 130 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
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| /netbsd/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 395 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
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| /netbsd/external/gpl3/gcc/dist/gcc/config/rs6000/ |
| H A D | rs6000-builtin.def | 1664 BU_ALTIVEC_OVERLOAD_X (ADDE, "adde")
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| /netbsd/external/gpl3/gcc.old/dist/gcc/config/rs6000/ |
| H A D | rs6000-builtin.def | 1664 BU_ALTIVEC_OVERLOAD_X (ADDE, "adde")
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| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 502 setOperationAction(ISD::ADDE, MVT::i32, Custom); in AArch64TargetLowering()
506 setOperationAction(ISD::ADDE, MVT::i64, Custom); in AArch64TargetLowering()
3134 case ISD::ADDE: in LowerADDC_ADDE_SUBC_SUBE()
4498 case ISD::ADDE: in LowerOperation()
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